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74F169SJX View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
Manufacturer
74F169SJX
Fairchild
Fairchild Semiconductor Fairchild
74F169SJX Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
Unit Loading/Fan Out
Pin Names
Description
CEP
CET
CP
P0–P3
PE
U/D
Q0–Q3
TC
Count Enable Parallel Input (Active LOW)
Count Enable Trickle Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Up-Down Count Control Input
Flip-Flop Outputs
Terminal Count Output (Active LOW)
U.L.
HIGH/LOW
1.0/1.0
1.0/2.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/0.6 mA
20 µA/1.2 mA
20 µA/0.6 mA
20 µA/0.6 mA
20 µA/0.6 mA
20 µA/0.6 mA
1 mA/20 mA
1 mA/20 mA
Functional Description
The 74F169 uses edge-triggered J-K type flip-flops and
has no constraints on changing the control or data input
signals in either state of the clock. The only requirement is
that the various inputs attain the desired state at least a
setup time before the rising edge of the clock and remain
valid for the recommended hold time thereafter. The paral-
lel load operation takes precedence over other operations,
as indicated in the Mode Select Table. When PE is LOW,
the data on the P0–P3 inputs enters the flip-flops on the
next rising edge of the clock. In order for counting to occur,
both CEP and CET must be LOW and PE must be HIGH;
the U/D input then determines the direction of counting.
The Terminal Count (TC) output is normally HIGH and goes
LOW, provided that CET is LOW, when a counter reaches
zero in the Count Down mode or reaches 15 for the
74F169 in the Count Up mode. The TC output state is not a
function of the Count Enable Parallel (CEP) input level.
Since the TC signal is derived by decoding the flip-flop
states, there exists the possibility of decoding spikes on
TC. For this reason the use of TC as a clock signal is not
recommended (see logic equations below).
1. Count Enable = CEP • CET • PE
2. Up: (74F169): TC = Q0 • Q1 • Q2 • Q3 • (Up) • CET
3. Down: TC = Q0 • Q1 • Q2 • Q3 • (Down) • CET
Mode Select Table
PE CEP CET U/D
Action on Rising
Clock Edge
L X X X Load (Pn Qn)
H L L H Count Up (Increment)
H L L L Count Down (Decrement)
H H X X No Change (Hold)
H X H X No Change (Hold)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
State Diagram
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