E28F004BX-B60 View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

E28F004BX-B60

4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY

Intel 

28F400BX-T B 28F004BX-T B

1 6 28F004BX Pin Descriptions

Symbol Type

Name and Function

A0 – A18

I ADDRESS INPUTS for memory addresses Addresses are internally latched during

a write cycle

A9

I

ADDRESS INPUT When A9 is at 12V the signature mode is accessed During this

mode A0 decodes between the manufacturer and device ID’s

DQ0 – DQ7 I O DATA INPUTS OUTPUTS Inputs array data on the second CE and WE cycle

during a program command Inputs commands to the command user interface when

CE and WE are active Data is internally latched during the write and program

cycles Outputs array Intelligent Identifier and status register data The data pins

float to tri-state when the chip is deselected or the outputs are disabled

CE

I CHIP ENABLE Activates the device’s control logic input buffers decoders and

sense amplifiers CE is active low CE high deselects the memory device and

reduces power consumption to standby levels If CE and RP are high but not at

a CMOS high level the standby current will increase due to current flow through the

CE and RP input stages

RP

I RESET DEEP POWERDOWN Provides Three-State control Puts the device in

deep power-down mode Locks the Boot Block from program erase

When RP is at logic high level and equals 6 5V maximum the Boot Block is locked

and cannot be programmed or erased

When RP e 11 4V minimum the Boot Block is unlocked and can be programmed

or erased

When RP is at a logic low level the Boot Block is locked the deep power-down

mode is enabled and the WSM is reset preventing any blocks from being

programmed or erased therefore providing data protection during power transitions

When RP transitions from logic low to logic high the flash memory enters the

read-array mode

OE

I OUTPUT ENABLE Gates the device’s outputs through the data buffers during a

read cycle OE is active low

WE

I WRITE ENABLE Controls writes to the Command Register and array blocks WE

is active low Addresses and data are latched on the rising edge of the WE pulse

VPP

VCC

GND

PROGRAM ERASE POWER SUPPLY For erasing memory array blocks or

programming data in each block

NOTE VPP k VPPLMAX memory contents cannot be altered

DEVICE POWER SUPPLY (5V g10% 5V g5%)

GROUND For all internal circuitry

NC

NO CONNECT Pin may be driven or left floating

DU

DON’T USE PIN Pin should not be connected to anything

10

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