AD8522AR-REEL View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD8522AR-REEL Datasheet PDF : 8 Pages
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AD8522
SDI
CLK
CS
LD
Sf/Hd B
A NC DB11 DB10
tCSS
tL D 1
SDO
SDI
CLK
LD
tDS tDH
tC H
tC L
tL D 2
RS
FS
VOUT
ZS
DB4 DB3 DB2 DB1 DB0
tCSH
tL D 2
tP D
tL D W
tS
tC L R W
tS
±1 LSB
ERROR BAND
tL D W
Figure 2. Timing Diagram
SERIAL INPUT REGISTER DATA FORMAT
Last
First
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 NC A
B Sf/Hd
Table I. Truth Table
Data Word
Ext Pins
Sf/Hd
B
A
LDA
LDB DAC Register
Hardware Load:
L
X
X
↓
↓
Loads DACA + DACB with Data from SR
L
X
X
↓
H
Loads DACA with Data from SR
L
X
X
H
↓
Loads DACB with Data from SR
L
X
X
H
H
No Load
Software Decode Load:
H
L
L
H
H
L
H
H
L
H
L
H
H
L
H
H
H
H
H
H
H
X
X
No Load
↓
↓
Loads DACB with Data from SR, See Note 1 Below
H
H
No Load
↓
↓
Loads DACA with Data from SR, See Note 1 Below
H
H
No Load
↓
↓
Loads DACA + DACB with Data from SR, See 1 Note Below
H
H
No Load
NOTES
1In software mode LDA and LDB perform the same function. They can be tied together or the unused pin should be tied high.
2External Pins LDA and LDB should always be high when shifting Data into the shift register.
3↓ symbol denotes negative transition.
1.6mA
SDO
1.6 VOLT
200µA
REV. A
Figure 3. AC Timing SDO Pin Load Circuit
–3–
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