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FIN3385 View Datasheet(PDF) - Fairchild Semiconductor

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FIN3385 Datasheet PDF : 21 Pages
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Transmitter AC Electrical Characteristics (Continued)
Over supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
Parameter
Transmitter Output Data Jitter (f=85MHz)(12)
Condition Min. Typ. Max. Unit
tTPPB0 Transmitter Output Pulse Position of Bit 0
-0.2
0
0.2
ns
tTPPB1 Transmitter Output Pulse Position of Bit 1
a-0.2
a
a+0.2 ns
tTPPB2
tTPPB3
tTPPB4
Transmitter Output Pulse Position of Bit 2
Transmitter Output Pulse Position of Bit 3
Transmitter Output Pulse Position of Bit 4
Figure 20
a1
f 7
2a-0.2
3a-0.2
4a-0.2
2a 2a+0.2 ns
3a 3a+0.2 ns
4a 4a+0.2 ns
tTPPB5 Transmitter Output Pulse Position of Bit 5
5a-0.2
5a 5a+0.2 ns
tTPPB6 Transmitter Output Pulse Position of Bit 6
6a-0.2
6a 6a+0.2 ns
tJCC
FIN3385 Transmitter Clock Out Jitter,
Cycle-to-Cycle, Figure 20
f=40MHz
f=65MHz
f=85MHz
350
370
210
230
ps
110
150
tTPLLS Transmitter Phase Lock Loop Set Time(13)
Figure 26(12)
10
ms
Notes:
11. Outputs of all transmitters stay in 3-STATE until power reaches 2V. Clock and data output begins to toggle 10ms
after VCC reaches 3.0V and /PwrDn pin is above 1.5V.
12. This output data pulse position works for both transmitters for TTL inputs, except the LVDS output bit mapping
difference (see Figure 18). Figure 20 shows the skew between the first data bit and clock output. A two-bit cycle
delay is guaranteed when the MSB is output from transmitter.
13. This jitter specification is based on the assumption that PLL has a reference clock with cycle-to-cycle input jitter
of less than 2ns.
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
9
www.fairchildsemi.com
 

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