FDN358P View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
Manufacturer
FDN358P Datasheet PDF : 4 Pages
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March 1998
FDN358P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
SuperSOTTM-3 P-Channel logic level enhancement mode
power field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited for
low voltage applications in notebook computers, portable
phones, PCMCIA cards, and other battery powered circuits
where fast switching, and low in-line power loss are needed
in a very small outline surface mount package.
-1.5 A, -30 V, RDS(ON) = 0.125 Ω @ VGS = -10 V
RDS(ON) = 0.20 Ω @ VGS = - 4.5 V.
High power version of industry SOT-23 package: identical
pin out to SOT-23; 30% higher power handling capability.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
SuperSOTTM-3
SuperSOTTM-6
SuperSOTTM-8
D
358
S
SuperSOT TM-3
G
SO-8
SOT-223
D
SOIC-16
G
S
Absolute Maximum Ratings TA = 25oC unless other wise noted
Symbol Parameter
VDSS
Drain-Source Voltage
VGSS
Gate-Source Voltage
ID
Drain/Output Current - Continuous
- Pulsed
PD
Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient (Note 1a)
RθJC
Thermal Resistance, Junction-to-Case (Note 1)
© 1998 Fairchild Semiconductor Corporation
FDN358P
-30
±20
-1.5
-5
0.5
0.46
-55 to 150
250
75
Units
V
V
A
W
°C
°C/W
°C/W
FDN358P Rev.D
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