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FDC37M603 View Datasheet(PDF) - SMSC -> Microchip

Part NameDescriptionManufacturer
FDC37M603 Enhanced Super I/O Controller with Infrared Support SMSC
SMSC -> Microchip SMSC
FDC37M603 Datasheet PDF : 182 Pages
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FUNCTIONAL DESCRIPTION
SUPER I/O REGISTERS
HOST PROCESSOR INTERFACE
The address map, shown below in Table 1,
shows the addresses of the different blocks of
the Super I/O immediately after power up. The
base addresses of the FDC, serial and parallel
ports can be moved via the configuration
registers. Some addresses are used to access
more than one register.
The host processor communicates with the
FDC37M60x through a series of read/write
registers. The port addresses for these registers
are shown in Table 1. Register access is
accomplished through programmed I/O or DMA
transfers. All registers are 8 bits wide. All host
interface output buffers are capable of sinking a
minimum of 24 mA.
Table 1 - Super I/O Block Addresses
LOGICAL
ADDRESS
BLOCK NAME
DEVICE
Base+(0-5) and +(7)
Floppy Disk
0
Base+(0-7)
Serial Port Com 1
4
Base1+(0-7)
Serial Port Com 2
5
Parallel Port
3
Base+(0-3)
SPP
Base+(0-7)
EPP
Base+(0-3), +(400-402)
ECP
Base+(0-7), +(400-402)
ECP+EPP+SPP
60, 64
KYBD
7
NOTES
IR Support
Note 1: Refer to the configuration register descriptions for setting the base address
11
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