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FDC37C672QFP View Datasheet(PDF) - SMSC -> Microchip

Part NameDescriptionManufacturer
FDC37C672QFP Enhanced Super I/O Controller with Fast IR SMSC
SMSC -> Microchip SMSC
FDC37C672QFP Datasheet PDF : 173 Pages
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Enhanced Super I/O Controller with Fast IR
Datasheet
17.1.5 CPU-to-Host Communication ........................................................................................................113
17.1.6 Host-to-CPU Communication ........................................................................................................113
17.1.7 KIRQ..............................................................................................................................................114
17.1.8 MIRQ .............................................................................................................................................114
17.1.9 Gate A20 .......................................................................................................................................114
17.2 External Keyboard and Mouse Interface...............................................................................................114
17.3 Keyboard Power Management .............................................................................................................114
17.3.1 Soft Power Down Mode.................................................................................................................114
17.3.2 Hard Power Down Mode ...............................................................................................................115
17.4 Interrupts ..............................................................................................................................................115
17.5 Memory Configurations.........................................................................................................................115
17.5.1 Register Definitions .......................................................................................................................115
17.5.2 Status Register ..............................................................................................................................115
17.6 External Clock Signal............................................................................................................................116
17.7 Default Reset Conditions ......................................................................................................................116
17.8 GATEA20 and Keyboard Reset ............................................................................................................116
17.9 Port 92 Fast GATEA20 and Keyboard Reset .......................................................................................117
17.9.1 Port 92 Register.............................................................................................................................117
17.9.2 8042 P12 and P16 Functions ........................................................................................................118
Chapter 18 System Management Interrupt (SMI) ................................................................................. 120
18.1 Registers ..............................................................................................................................................120
18.1.1 SMI Enable Registers....................................................................................................................120
18.1.2 SMI Status Registers.....................................................................................................................120
Chapter 19 Configuration ...................................................................................................................... 121
19.1 System Elements..................................................................................................................................121
19.1.1 Primary Configuration Address Decoder .......................................................................................121
19.1.2 Entering the Configuration State....................................................................................................121
19.1.3 Exiting the Configuration State ......................................................................................................122
19.2 Configuration Sequence .......................................................................................................................122
19.2.1 Enter Configuration Mode..............................................................................................................122
19.2.2 Configuration Mode .......................................................................................................................122
19.2.3 Exit Configuration Mode ................................................................................................................122
19.2.4 Programming Example ..................................................................................................................123
19.2.5 Chip Level (Global) Control/Configuration Registers [0x00-0x2F] .................................................125
19.2.6 Logical Device Configuration/Control Registers [0x30-0xFF] ........................................................128
19.2.7 Note A. Logical Device IRQ and DMA Operation ..........................................................................132
19.2.8 SMSC Defined Logical Device Configuration Registers ................................................................132
Chapter 20 Operational Description...................................................................................................... 143
20.1 Maximum Guaranteed Ratings*............................................................................................................143
20.2 DC Electrical Characteristics ................................................................................................................143
Chapter 21 Timing Diagrams ................................................................................................................146
Chapter 22 ECP Parallel Port Timing.................................................................................................... 164
Chapter 23 Package Outlines ...............................................................................................................172
List of Figures
Figure 2.1 - FDC37C672 100 Pin QFP ........................................................................................................................10
Figure 2.2 - FDC37C672 100 Pin TQFP ......................................................................................................................11
Figure 4.1 - FDC37C672 Block Diagram......................................................................................................................16
Figure 11.1 - IR Interface Block Diagram .....................................................................................................................79
Figure 17.1 - Keyboard and Mouse Interface.............................................................................................................112
Figure 17.2 - Gate A20 Turn-On Sequence Timing....................................................................................................119
Figure 21.1 - IOW Timing for Port 92 .........................................................................................................................147
Figure 21.2 - Power-Up Timing ..................................................................................................................................147
Figure 21.3 - ISA Write...............................................................................................................................................148
Figure 21.4 - ISA Read ..............................................................................................................................................149
Figure 21.5 - Internal 8042 CPU Timing.....................................................................................................................150
Figure 21.6 - Input Clock Timing ................................................................................................................................151
SMSC FDC37C672
Page 6
DATASHEET
Rev. 10-29-03
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