M48Z512AV-85PM1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M48Z512AV-85PM1 Datasheet PDF : 21 Pages
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M48Z512A, M48Z512AY, M48Z512AV
2
Operating modes
Operating modes
The M48Z512A/Y/V also has its own power-fail detect circuit. The control circuitry constantly
monitors the single VCC supply for an out of tolerance condition. When VCC is out of
tolerance, the circuit WRITE protects the SRAM, providing a high degree of data security in
the midst of unpredictable system operation brought on by low VCC. As VCC falls below the
switchover voltage (VSO), the control circuitry connects the battery which maintains data
until valid power returns.
The ZEROPOWER® RAM replaces industry standard SRAMs. It provides the nonvolatility of
PROMs without any requirement for special WRITE timing or limitations on the number of
) - Obsolete Product(s) Note:
Obsolete Product(s 2.1
WRITEs that can be performed.
Table 2. Operating modes
Mode
VCC
E
G
W
Deselect
4.75 to 5.5 V
VIH
X
X
WRITE
READ
or
4.5 to 5.5 V
or
VIL
X
VIL
VIL
VIL
VIH
READ
3.0 to 3.6 V
VIL
VIH
VIH
Deselect
VSO to VPFD (min)(1)
X
X
X
Deselect
≤ VSO(1)
X
X
X
1. X = VIH or VIL; VSO = battery backup switchover voltage.
DQ0-DQ7
Power
High Z
DIN
DOUT
High Z
High Z
High Z
Standby
Active
Active
Active
CMOS standby
Battery backup mode
See Table 10 on page 16 for details.
READ mode
The M48Z512A/Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
4,194,304 locations in the static storage array. Thus, the unique address specified by the 19
address inputs defines which one of the 524,288 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (tAVQV) after the last
address input signal is stable, providing that the E (chip enable) and G (output enable)
access times are also satisfied. If the E and G access times are not met, valid data will be
available after the later of chip enable access time (tELQV) or output enable access Time
(tGLQV). The state of the eight three-state data I/O signals is controlled by E and G. If the
outputs are activated before tAVQV, the data lines will be driven to an indeterminate state
until tAVQV. If the address inputs are changed while E and G remain low, output data will
remain valid for output data hold time (tAXQX) but will go indeterminate until the next address
access.
Doc ID 5146 Rev 9
7/21
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