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M48Z512AV-70PM1(2010) View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
M48Z512AV-70PM1
(Rev.:2010)
ST-Microelectronics
STMicroelectronics ST-Microelectronics
M48Z512AV-70PM1 Datasheet PDF : 21 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
M48Z512A, M48Z512AY, M48Z512AV
Operating modes
Table 4. WRITE mode AC characteristics
Symbol
Parameter(1)
M48Z512A/Y
–70
Min Max
M48Z512A/Y/V
–85
Unit
Min Max
tAVAV WRITE cycle time
70
85
ns
tAVWL Address valid to WRITE enable low
0
0
ns
tAVEL Address valid to chip enable low
0
0
ns
tWLWH WRITE enable pulse width
55
65
ns
tELEH Chip enable low to chip enable high
55
75
ns
tWHAX WRITE enable high to address transition
5
5
ns
tEHAX Chip enable high to address transition
15
15
ns
tDVWH Input valid to WRITE enable high
30
35
ns
tDVEH Input valid to chip enable high
30
35
ns
tWHDX WRITE enable high to input transition
0
0
ns
tEHDX Chip enable high to input transition
tWLQZ(2)(3) WRITE enable low to output Hi-Z
10
10
ns
25
30
ns
tAVWH Address valid to WRITE enable high
65
75
ns
tAVEH Address valid to chip enable high
65
tWHQX(2)(3) WRITE enable high to output transition
5
75
ns
5
ns
1. Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V
or 3.0 to 3.6 V (except where noted).
2. CL = 5 pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid VCC applied, the M48Z512A/Y/V operates as a conventional BYTEWIDEâ„¢ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect,
WRITE protecting itself tWP after VCC falls below VPFD. All outputs become high impedance,
and all inputs are treated as “don't care.â€
If power fail detection occurs during a valid access, the memory cycle continues to
completion. If the memory cycle fails to terminate within the time tWP, WRITE protection
takes place. When VCC drops below VSO, the control circuit switches power to the internal
energy source which preserves data.
The internal coin cell will maintain data in the M48Z512A/Y/V after the initial application of
VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system
power returns and VCC rises above VSO, the battery is disconnected, and the power supply
is switched to external VCC. WRITE protection continues for tER after VCC reaches VPFD to
allow for processor stabilization. After tER, normal RAM operation can resume.
For more information on battery storage life refer to the application note AN1012.
Doc ID 5146 Rev 8
11/21
 

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