Operating modes
M48Z512A, M48Z512AY, M48Z512AV
Figure 6. WRITE enable controlled, WRITE AC waveforms
A0-A18
E
W
DQ0-DQ7
tAVEL
tAVAV
VALID
tAVWH
tAVWL
tWLWH
tWLQZ
tWHDX
DATA INPUT
tDVWH
1. Output enable (G) = high.
Figure 7. Chip enable controlled, WRITE AC waveforms
tWHAX
tWHQX
AI01222
A0-A18
E
W
DQ0-DQ7
tAVEL
tAVWL
1. Output enable (G) = high.
tAVAV
VALID
tAVEH
tELEH
tEHAX
tEHDX
DATA INPUT
tDVEH
AI01223
10/21
Doc ID 5146 Rev 8