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M48Z512A-70PM1(2006) View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
M48Z512A-70PM1
(Rev.:2006)
ST-Microelectronics
STMicroelectronics ST-Microelectronics
M48Z512A-70PM1 Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Operating modes
M48Z512A M48Z512AY M48Z512AV
Table 4. READ mode ac characteristics
Symbol
Parameter(1)
M48Z512A/Y
-70
M48Z512A/Y/V
-85
Unit
Min Max Min Max
tAVAV READ Cycle Time
70
85
ns
tAVQV Address Valid to Output Valid
70
85
ns
tELQV Chip Enable low to Output Valid
70
85
ns
tGLQV Output Enable low to Output Valid
35
45
ns
tELQX(2) Chip Enable low to Output Transition
5
5
ns
tGLQX(2) Output Enable low to Output Transition
5
5
ns
tEHQZ(2) Chip Enable high to Output Hi-Z
30
35
ns
tGHQZ(2) Output Enable high to Output Hi-Z
20
25
ns
tAXQX Address Transition to Output Transition
5
5
ns
1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or -40 to 85°C; VCC = 4.75 to 5.5V, 4.5 to 5.5V,
or 3.0 to 3.6V (except where noted).
2. CL = 5pF.
2.2
WRITE mode
The M48Z512A/Y/V is in the WRITE mode whenever W and E are active. The start of a
WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated
by the earlier rising edge of W or E.
The addresses must be held valid throughout the cycle. E or W must return high for a
minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE
cycle. Data-in must be valid tDVEH or tDVWH prior to the end of WRITE and remain valid for
tEHDX or tWHDX afterward. G should be kept high during WRITE cycles to avoid bus
contention; although, if the output bus has been activated by a low on E and G, a low on W
will disable the outputs tWLQZ after W falls.
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