FAN5019B View Datasheet(PDF) - Fairchild Semiconductor
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FAN5019B Datasheet PDF : 30 Pages
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PRODUCT SPECIFICATION
FAN5019B
4. Compute the relative values for RCS1, RCS2, and RTH
using:
rCS2
=
(A
− B)×r1 ×r2 − A×(1− B)
A×(1− B) ×r1 − B×(1−
×r2 + B×(1−
A) ×r2 −(A−
A)
B)
× r1
rCS1 =
(1 − A)
1− A
(8)
1 − rCS 2 r1 − rCS 2
rTH =
1
1 −1
1 − rCS 2 rCS 1
5. Calculate RTH = rTH x RCS, then select the closest value
of thermistor available. Also compute a scaling factor k
based on the ratio of the actual thermistor value used
relative to the computed one:
k = RTH ( ACTUAL)
(9)
RTH (CALCULATED)
6. Finally, calculate values for RCS1 and RCS2 using the
following:
RCS1 = RCS × k × rCS1
(10)
RCS 2 = RCS × ((1− k ) + (k × rCS 2 ))
For this example, RCS has been chosen to be 100kΩ, so we
start with a thermistor value of 100kΩ. Looking through
available 0603 size thermistors, we find a Panasonic
ERT-J1VV104J NTC thermistor with A = 0.2954 and
B = 0.05684. From these we compute RCS1 = 0.3304,
RCS2 = 0.7426 and RTH = 1.165. Solving for RTH yields
116.5 kΩ, so we choose 100kΩ, making k = 0.8585. Finally,
we find RCS1 and RCS2 to be 28.4kΩ and 77.9kΩ. Choosing
the closest 1% resistor values yields a choice of 35.7kΩ and
73.2kΩ.
Output Offset
Intel’s specification requires that at no load the nominal out-
put voltage of the regulator be offset to a lower value than
the nominal voltage corresponding to the VID code. The off-
set is set by a constant current source flowing out of the FB
pin (IFB) and flowing through RB. The value of RB can be
found using Equation 11:
RB
=
VVID − VONL
I FB
(11)
COUT Selection
The required output decoupling for the regulator is typically
recommended by Intel for various processors and platforms.
There are also some simple design guidelines to determine
what is required. These guidelines are based on having both
bulk and ceramic capacitors in the system.
The first step is to select the total amount of ceramic capaci-
tance. This is based on the number and type of capacitor to
be used. The best location for ceramics is inside the socket,
with 12 to 18 of size 1206 being the physical limit. Others
can be placed along the outer edge of the socket as well.
Combined ceramic values of 200µF–300µF are recom-
mended, usually made up of multiple 10µF or 22µF
capacitors. Select the number of ceramics and find the total
ceramic capacitance (CZ).
Next, there is an upper limit imposed on the total amount of
bulk capacitance (CX) when one considers the VID on-the-
fly voltage stepping of the output (voltage step VV in time tV
with error VERR) and a lower limit based on meeting the crit-
ical capacitance for load release for a given maximum load
step ΔIO:
CX (MIN)
≥
⎜⎜⎝⎛
n
L × ΔIO
× RO ×VVID
− CZ ⎟⎟⎠⎞
(12)
CX ( MAX)
≤
L
nK2RO2
×
VV
VVID
×
⎜⎛
⎜⎜⎝
1+ ⎜⎜⎝⎛tV
VVID
VV
×
nKRO
L
⎟⎟⎠⎞2
− 1⎟⎟⎟⎠⎞
−
CZ
where
(13)
K
=
−
ln
⎜⎜⎝⎛
VVERR
VV
⎟⎟⎠⎞
To meet the conditions of these expressions and transient
response, the ESR of the bulk capacitor bank (RX) should be
less than two times the droop resistance, RO. If the CX(MIN)
is larger than CX(MAX), the system will not meet the VID
on-the-fly specification and may require the use of a smaller
inductor or more phases (and may have to increase the
switching frequency to keep the output ripple the same).
For our example, 22 10µF 1206 MLC capacitors (CZ =
220µF) were used. The VID on-the-fly step change is
250mV in 150µs with a setting error of 2.5mV. Solving for
the bulk capacitance yields:
RB
= 1.5V − 1.480V
15μA
= 1.33kΩ
The closest standard 1% resistor value is 1.33 kΩ.
REV. 1.0.0 Jul/15/05
21
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