FAN5018B
PRODUCT SPECIFICATION
This limit can be adjusted by changing the ramp voltage VR.
Do not set the per-phase limit lower than the average per-
TB = (1.0mΩ + 0.6mΩ −1.3mΩ)×6.56mF = 1.97μs
phase current (ILIM/n).
There is also a per phase initial duty cycle limit determined
by:
TC
=
VRT
× ⎜⎜⎝⎛ L −
AD × RDS
2 × f SW
VVID × RE
⎟⎟⎠⎞
(28)
DMAX
= D × VCOMP( MAX ) − VBIAS
VRT
(24)
For this example, the maximum duty cycle is found to be
0.2696.
Feedback Loop Compensation Design
Optimized compensation of the FAN5018B allows the best
possible response of the regulator’s output to a load change.
The basis for determining the optimum compensation is to
make the regulator and output decoupling appear as an
output impedance that is entirely resistive over the widest
possible frequency range, including DC, and equal to the
droop resistance (RO). With the resistive output impedance,
the output voltage will droop in proportion with the load
current at any load current slew rate; this ensures the optimal
positioning and allows the minimization of the output
decoupling.
With the multimode feedback structure of the FAN5018B,
the feedback compensation should be set to make the con-
verter’s output impedance work in conjunction with the out-
put decoupling to meet this goal. The output inductor and
decoupling capacitors (output filter) create several poles and
zeros that require compensation.
TC
=
0.974V
×
⎜⎛ 650nH
⎝
−
5 × 6.95mΩ
2 × 228kHz
⎟⎞
⎠
1.5V × 55.3mΩ
=
6.86μs
TD
=
CX
CX
× (RO
× CZ
×
R
2
O
− R')+ CZ
× RO
(29)
TD
=
6.56mF
6.56mF × 220μF × (1.3mΩ)2
× (1.3mΩ − 0.6mΩ) + 220μF
×1.3mΩ
=
500ns
where, for the FAN5018B, R' is the PCB resistance from the
bulk capacitors to the ceramics and where RDS is approxi-
mately the total low-side MOSFET ON resistance per phase
at 25ºC. For this example, AD is 5, VRT equals 0.974V, R' is
approximately 0.6mΩ (assuming a 4-layer motherboard) and
LX is 375pH for the eight Al-Poly capacitors.
The compensation values can then be solved using the fol-
lowing equations:
CA
=
n × RO ×TA
RE × RB
(30)
CA
=
3×1.3mΩ × 4.79μs
55.3mΩ ×1.33kΩ
=
253 pF
A type-III compensator on the voltage feedback is adequate
for proper compensation of the output filter. The expressions
given in Equations 25–29 are intended to yield an optimal
RA
=
TC
CA
=
6.86μs
253 pF
=
27.1kΩ
(31)
starting point for the design; some adjustments may be nec-
essary to account for PCB and component parasitic effects
(see the Tuning Procedure for the FAN5018B section).
CB
=
TB
RB
= 1.97μs
1.33kΩ
= 1.48nF
(32)
The first step is to compute the time constants for all of the
poles and zeros in the system:
CFB
=
TD
RA
=
500ns
27.1kΩ
= 18.5 pF
(33)
( ) RE
=
n × RO
+
AD
× RDS
+
RL ×VRT
VVID
+
2×L× 1−n×D ×VRT
n×CX ×RO ×VVID
(25)
RE
= 3 ×1.3mΩ + 5 × 5.95mΩ + 1.6mΩ × 0.974V
1.5V
+
2 × 650nH × (1 − 0.375)× 0.974V
3 × 6.56mF ×1.3mΩ ×1.5V
= 55.3mΩ
TA
=
CX
× (RO
− R')+
LX
RO
×
RO − R'
RX
(26)
TA
=
6.56mF
× (1.3mΩ − 0.6mΩ) +
375 pH
1.3mΩ
× 1.3mΩ − 0.6mΩ
1.0mΩ
=
4.79μs
TB = (RX + R'−RO )×CX
(27)
24
REV. 1.0.0 Jul/15/05