Q67100-H3525 View Datasheet(PDF) - Infineon Technologies

Part Name

Description

Manufacturer

Q67100-H3525

4 Kbit (512 × 8 bit) Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus, Page Protection Mode™

Infineon Technologies 

SLx 24C04/P

The conventions for the serial clock line and the bidirectional data line are shown in

figure 4.

SCL

1

2

8

9

1

9

SDA

ACK

ACK

START Condition

Data allowed

to Change

Acknowledge

STOP Condition

IED02128

Figure 4

I2C-Bus Timing Conventions for START Condition, STOP Condition, Data Valida-

tion and Transfer of Acknowledge ACK

Standby

START Condition

STOP Condition

Acknowledge

Data Transfer

Mode in which the bus is not busy (no serial transmission, no

programming): both clock (SCL) and data line (SDA) are in high

state. The device enters the standby mode after a STOP condition

or after a programming cycle.

High to low transition of SDA when SCL is high, preceding all

commands.

Low to high transition of SDA when SCL is high, terminating all

communications. A STOP condition initiates an EEPROM

programming cycle. A STOP condition after reading a data byte

from the EEPROM initiates the Standby mode.

A successful reception of eight data bits is indicated by the

receiver by pulling down the SDA line during the following clock

cycle of SCL (ACK). The transmitter on the other hand has to

release the SDA line after the transmission of eight data bits.

The EEPROM as the receiving device responds with an

acknowledge, when addressed. The master, on the other side,

acknowledges each data byte transmitted by the EEPROM and

can at any time end a read operation by releasing the SDA line (no

ACK) followed by a STOP condition.

Data must change only during low SCL state, data remains valid

on the SDA bus during high SCL state. Nine clock pulses are

required to transfer one data byte, the most significant bit (MSB)

is transmitted first.

Semiconductor Group

8

1998-07-27

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