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EX256-PCS128PP View Datasheet(PDF) - Actel Corporation

Part Name
Description
Manufacturer
EX256-PCS128PP
ACTEL
Actel Corporation ACTEL
EX256-PCS128PP Datasheet PDF : 36 Pages
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eX Family FPGAs
Clock Resources
Actels high-drive routing structure provides three clock
networks. The first clock, called HCLK, is hardwired from
the HCLK buffer to the clock select MUX in each R-Cell.
HCLK cannot be connected to combinational logic. This
provides a fast propagation path for the clock signal,
enabling the 3.9ns clock-to-out (pad-to-pad) performance of
the eX devices. The hard-wired clock is tuned to provide a
clock skew of less than 0.1ns worst case.
The remaining two clocks (CLKA, CLKB) are global clocks
that can be sourced from external pins or from internal
logic signals within the eX device. CLKA and CLKB may be
connected to sequential cells or to combinational logic. If
CLKA or CLKB is sourced from internal logic signals then
the external clock pin cannot be used for any other input
and must be tied low or high. Figure 5 describes the clock
circuit used for the constant load HCLK. Figure 6 describes
the CLKA and CLKB circuit used in eX devices.
HCLKBUF
Constant Load
Clock Network
Figure 5 eX HCLK Clock Pad
Clock Network
From Internal Logic
CLKBUF
CLKBUFI
CLKINT
CLKINTI
Figure 6 eX Routed Clock Buffer
Other Architectural Features
Technology
Actels eX family is implemented on a high-voltage twin-well
CMOS process using 0.22µ design rules. The metal-to-metal
antifuse is made up of a combination of amorphous silicon
and dielectric material with barrier metals and has an on
state resistance of 25with a capacitance of 1.0 fF for low
signal impedance.
Performance
The combination of architectural features described above
enables eX devices to operate with internal clock
frequencies exceeding 350 MHz for very fast execution of
complex logic functions. Thus, the eX family is an optimal
platform upon which to integrate the functionality
previously contained in CPLDs. In addition, designs that
previously would have required a gate array to meet
performance goals can now be integrated into an eX device
with dramatic improvements in cost and time to market.
Using timing-driven place-and-route tools, designers can
achieve highly deterministic device performance.
I/O Modules
Each I/O on an eX device can be configured as an input, an
output, a tristate output, or a bidirectional pin. Even without
the inclusion of dedicated I/O registers, these I/Os, in
combination with array registers, can achieve clock-to-out
(pad-to-pad) timing as fast as 3.9ns. I/O cells that have
embedded latches and flip-flops require instantiation in HDL
code; this is a design complication not encountered in eX
FPGAs. Fast pin-to-pin timing ensures that the device will
have little trouble interfacing with any other device in the
system, which in turn enables parallel design of system
components and reduces overall design time. See Table 1 for
more information.
Table 1 I/O Features
Function Description
Input Buffer
Threshold
Selection
Flexible
Output
Driver
Output
Buffer
Power Up
TTL/3.3V LVTTL
2.5V LVCMOS 2
3.3V LVTTL
5.0V TTL/CMOS
Hot-SwapCapability
I/O on an unpowered device does not
sink current
Can be used for cold sparing
Selectable on an individual I/O basis
Individually selectable low-slew option
Individually selectable pull ups and pull
downs during power up (default is to power
up in tristate)
Enables deterministic power up of device
VCCA and VCCI can be powered in any order
Hot Swapping
eX I/Os are configured to be hot swappable. During power
up/down (or partial up/down), all I/Os are tristated. VCCA
and VCCI do not have to be stable during power up/down,
and they do not require a specific power-up or power-down
sequence in order to avoid damage to the eX devices. After
the eX device is plugged into an electrically active system,
the device will not degrade the reliability of or cause
damage to the host system. The devices output pins are
driven to a high impedance state until normal chip
v3.0
5
 

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