E-ETC5054D-X/HTR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
E-ETC5054D-X/HTR Datasheet PDF : 18 Pages
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ETC5054 - ETC5057
FUNCTIONAL DESCRIPTION
POWER-UP
When power is first applied, power-on reset cir-
cuitry initializes the device and places it into
the power-down mode. All non-essential circuits
are deactivated and the DX and VFRO outputs are
put in high impedance states. To power-up the
device, a logical low level or clock must be ap-
plied to the MCLKR/PDN pin and FSX and/or FSR
pulses must be present. Thus, 2 power-down
control modes are available. The first is to pull the
MCLKR/PDN pin high ; the alternative is to hold
both FSX and FSR inputs continuously low. The
device will power-down approximately 2 ms after
the last FSX or FSR pulse. Power-up will occur on
the first FSX or FSR pulse. The TRI-STATE PCM
data output, DX, will remain in the high impedance
state until the second FSX pulse.
SYNCHRONOUS OPERATION
For synchronous operation, the same master
clock and bit clock should be used for both the
transmit and receive directions. In this mode, a
clock must be applied to MCLKX and the
MCLKR/PDN pin can be used as a power-down
control. A low level on MCLKR/PDN powers up
the device and a high level powers down the de-
vice. In either case, MCLKX will be selected as
the master clock for both the transmit and receive
circuits. A bit clock must also be applied to BCLKX
and the BCLKR/CKSEL can be used to select the
proper internal divider for a master clock of 1.536
MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz
operation, the device automatically compensates
for the 193rd clock pulse each frame. With a fixed
level on the BCLKR/CLKSEL pin, BCLKX will be
selected as the bit clock for both the transmit and
receive directions. Table 1 indicates the frequen-
cies of operation which can be selected, depend-
ing on the state of BCLKR/CLKSEL. In this syn-
chronous mode, the bit clock, BCLKX, may be
from 64 kHz to 2.048 MHz, but must be synchro-
nous with MCLKX.
Each FSX pulse begins the encoding cycle and
the PCM data from the previous encode cycle is
shifted out of the enabled DX output on the posi-
tive edge of BCLKX. After 8 bit clock periods, the
Table 1: Selection of Master Clock Frequencies.
BCLKR/CLKSEL
Clocked
0
Master Clock Frequency
Selected
ETC5057
ETC5054
2.048 MHz
1.536 MHz or
1.544 MHz
1.536 MHz or
1.544 MHz
2.048 MHz
1 (or open circuit) 2.048 MHz
1.536 MHz or
1.544 MHz
4/18
TRI-STATE DX output is returned to a high im-
pedance state. With and FSR pulse, PCM data is
latched via the DR input on the negative edge of
BCLKX (or BCLKR if running). FSX and FSR must
be synchronous with MCLKX/R.
ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit
and receive clocks may be applied, MCLKX and
MCLKR must be 2.048 MHz for the ETC5057, or
1.536 MHz, 1.544 MHz for the ETC5054, and
need not be synchronous. For best transmission
performance, however, MCLKR should be syn-
chronous with MCLKX, which is easily achieved
by applying only static logic levels to the
MCLKR/PDN pin. This will automatically connect
MCLKX to all internal MCLKR functions (see pin
description). For 1.544 MHz operation, the device
automatically compensates for the 193rd clock
pulse each frame. FSX starts each encoding cycle
and must be synchronous with MCLKX and
BCLKX. FSR starts each decoding cycle and must
be synchronous with BCLKR. BCLKR must be a
clock, the logic levels shown in table 1 are not
valid in asynchronous mode. BCLKX and BCLKR
may operate from 64 kHz to 2.048 MHz.
SHORT FRAME SYNC OPERATION
The device can utilize either a short frame sync
pulse or a long frame sync pulse. Upon power in-
itialization, the device assumes a short frame
mode. In this mode, both frame sync pulses, FSX
and FSR, must be one bit clock period long, with
timing relationships specified in figure 2. With FSX
high during a falling edge of BCLKX the next ris-
ing edge of BCLKX enables the DX TRI-STATE
output buffer, which will output the sign bit. The
following seven rising edges clock out the remain-
ing seven bits, and the next falling edge disables
the DX output. With FSR high during a falling edge
of BCLKR (BCLKX in synchronous mode), the
next falling edge of BCLKR latches in the sign bit.
The following seven falling edges latch in the
seven remaining bits. Both devices may utilize the
short frame sync pulse in synchronous or asyn-
chronous operating mode.
LONG FRAME SYNC OPERATION
To use the long frame mode, both the frame sync
pulses, FSX and FSR, must be three or more bit
clock periods long, with timing relationships speci-
fied in figure 3. Based on the transmit frame sync,
FSX, the device will sense whether short or long
frame sync pulses are being used. For 64 kHz op-
eration, the frame sync pulse must be kept low for
a minimum of 160 ns (see fig. 1). The DX TRI-
STATE output buffer is enabled with the rising
edge of FSX or the rising edge of BCLKX, which-
ever comes later, and the first bit clocked out is
the sign bit. The following seven BCLKX rising
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