EN29LV160C View Datasheet(PDF) - Eon Silicon Solution Inc.

Part Name

Description

Manufacturer

EN29LV160C

16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only

Eon Silicon Solution Inc. 

EN29LV160C

limit is exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read

mode.

Chip Erase Command

Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by

the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not

require the system to preprogram prior to erase. The Embedded Erase algorithm automatically

preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or timings during these operations. The Command

Definitions table shows the address and data requirements for the chip erase command sequence.

Any commands written to the chip during the Embedded Chip Erase algorithm are ignored.

The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write

Operation Status” for information on these status bits. When the Embedded Erase algorithm is

complete, the device returns to reading array data and addresses are no longer latched.

Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables

in “AC Characteristics” for parameters, and to the Chip/Sector Erase Operation Timings for timing

waveforms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing

two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed

by the address of the sector to be erased, and the sector erase command. The Command Definitions

table shows the address and data requirements for the sector erase command sequence.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other

commands are ignored.

When the Embedded Erase algorithm is complete, the device returns to reading array data and

addresses are no longer latched. The system can determine the status of the erase operation by using

DQ7, DQ6, or DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4

illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the

“AC Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for

timing waveforms.

Erase Suspend / Resume Command

The Erase Suspend command allows the system to interrupt a sector erase operation and then read

data from, or program data to, any sector not selected for erasure. This command is valid only during

the sector erase operation. The Erase Suspend command is ignored if written during the chip erase

operation or Embedded Program algorithm. Addresses are don’t-cares when writing the Erase

Suspend command.

When the Erase Suspend command is written during a sector erase operation, the device requires a

maximum of 20 µs to suspend the erase operation.

After the erase operation has been suspended, the system can read array data from or program data to

any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.)

Normal read and write timings and command definitions apply. Reading at any address within erase-

suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2

together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation

Status” for information on these status bits.

This Data Sheet may be revised by subsequent versions

16

or modifications due to changes in technical specifications.

© 2004 Eon Silicon Solution, Inc.,

Rev. C, Issue Date: 2011/10/26

www.eonssi.com

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