EN25Q16-100GIP View Datasheet(PDF) - Eon Silicon Solution Inc.

Part Name

Description

Manufacturer

EN25Q16-100GIP

16 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

Eon Silicon Solution Inc. 

OPERATING FEATURES

EN25Q16

Standard SPI Modes

The EN25Q16 is accessed through an SPI compatible bus consisting of four signals: Serial Clock

(CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation

Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as

shown in Figure 3, concerns the normal state of the CLK signal when the SPI bus master is in standby

and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For

Mode 3 the CLK signal is normally high. In either case data input on the DI pin is sampled on the rising

edge of the CLK. Data output on the DO pin is clocked out on the falling edge of CLK.

Figure 3. SPI Modes

Dual SPI Instruction

The EN25Q16 supports Dual SPI operation when using the “ Dual Output Fast Read and Dual I/ O

FAST_READ “ (3Bh and BBh) instructions. These instructions allow data to be transferred to or from

the Serial Flash memory at two to three times the rate possible with the standard SPI. The Dual Read

instructions are ideal for quickly downloading code from Flash to RAM upon power-up (code-shadowing)

or for application that cache code-segments to RAM for execution. The Dual output feature simply

allows the SPI input pin to also serve as an output during this instruction. When using Dual SPI

instructions the DI and DO pins become bidirectional I/O pins; DQ0 and DQ1. All other operations use

the standard SPI interface with single output signal.

Quad SPI Instruction

The EN25Q16 supports Quad SPI operation when using the Quad I/O Fast Read (EBh). This

instruction allows data to be transferred to or from the Serial Flash memory at four to six times the rate

possible with the standard SPI. The Quad Read instruction offer a significant improvement in

continuous and random access transfer rates allowing fast code-shadowing to RAM or for application

that cache code-segments to RAM for execution. When using Quad SPI instruction the DI and DO pins

become bidirectional I/O pins; DQ0 and DQ1, and the WP# and NC pins become DQ2 and DQ3

respectively.

Page Programming

To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and

a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal

Program cycle (of duration tPP).

To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed

at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page

of memory.

Sector Erase, Block Erase and Chip Erase

The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the

bytes of memory need to have been erased to all 1s (FFh). This can be achieved a sector at a time,

using the Sector Erase (SE) instruction, a block at a time using the Block Erase (BE) instruction or

This Data Sheet may be revised by subsequent versions

7

or modifications due to changes in technical specifications.

©2004 Eon Silicon Solution, Inc.,

Rev. E, Issue Date: 2009/10/21

www.eonssi.com

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