EN25Q16-100HIP View Datasheet(PDF) - Eon Silicon Solution Inc.

Part Name

Description

Manufacturer

EN25Q16-100HIP

16 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

Eon Silicon Solution Inc. 

EN25Q16

Quad Input/Output FAST_READ (EBh)

The Quad Input/Output FAST_READ (EBh) instruction is similar to the Dual I/O Fast Read (BBh)

instruction except that address and data bits are input and output through four pins. DQ0, DQ1, DQ2 and

DQ3 and four Dummy clocks are required prior to the data output. The Quad I/O dramatically reduces

instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI.

The Quad Input/Output FAST_READ (EBh) instruction enable quad throughput of Serial Flash in read

mode. The address is latching on rising edge of CLK, and data of every four bits (interleave on 4 I/O

pins) shift our on the falling edge of CLK at a maximum frequency FR. The first address can be any

location. The address is automatically increased to the next higher address after each byte data is

shifted out, so the whole memory can be read out at a single Quad Input/Output FAST_READ

instruction. The address counter rolls over to 0 when the highest address has been reached. Once

writing Quad Input/Output FAST_READ instruction, the following address/dummy/data out will perform

as 4-bit instead of previous 1-bit.

The sequence of issuing Quad Input/Output FAST_READ (EBh) instruction is: CS# goes low ->

sending Quad Input/Output FAST_READ (EBh) instruction -> 24-bit address interleave on DQ3, DQ2,

DQ1 and DQ0 -> 6 dummy cycles -> data out interleave on DQ3, DQ2, DQ1 and DQ0 -> to end Quad

Input/Output FAST_READ (EBh) operation can use CS# to high at any time during data out, as shown

in Figure 12.

Figure 12. Quad Input / Output Fast Read Instruction Sequence Diagram

Another sequence of issuing Quad Input/Output FAST_READ (EBh) instruction especially useful in

random access is : CS# goes low -> sending Quad Input/Output FAST_READ (EBh) instruction -> 24-

bit address interleave on DQ3, DQ2, DQ1 and DQ0 -> performance enhance toggling bit P[7:0] -> 4

dummy cycles -> data out interleave on DQ3, DQ2, DQ1 and DQ0 till CS# goes high -> CS# goes low

(reduce Quad Input/Output FAST_READ (EBh) instruction) -> 24-bit random access address, as shown

in Figure 13.

In the performance – enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0] = A5h, 5Ah,

F0h or 0Fh can make this mode continue and reduce the next Quad Input/Output FAST_READ (EBh)

instruction. Once P[7:4] is no longer toggling with P[3:0] ; likewise P[7:0] = FFh, 00h, AAh or 55h. And

afterwards CS# is raised, the system then will escape from performance enhance mode and return to

normal operation.

While Program/ Erase/ Write Status Register is in progress, Quad Input/Output FAST_READ (EBh)

instruction is rejected without impact on the Program/ Erase/ Write Status Register current cycle.

This Data Sheet may be revised by subsequent versions

19

or modifications due to changes in technical specifications.

©2004 Eon Silicon Solution, Inc.,

Rev. E, Issue Date: 2009/10/21

www.eonssi.com

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