EDS5104ABTA-75 View Datasheet(PDF) - Elpida Memory, Inc

Part Name

Description

Manufacturer

EDS5104ABTA-75

512M bits SDRAM / 54-pin TSOP

Elpida Memory, Inc 

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Refresh

Auto-refresh

All the banks must be precharged before executing an auto-refresh command. Since the auto-refresh command

updates the internal counter every time it is executed and determines the banks and the ROW addresses to be

refreshed, external address specification is not required. The refresh cycles are required to refresh all the ROW

addresses within tREF (max.). The output buffer becomes High-Z after auto-refresh start. In addition, since a

precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by

the precharge command is not required.

Self-refresh

After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During self-

refresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a

self-refresh exit command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or

within tREF (max.) period on the condition 1 and 2 below.

1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to

all refresh addresses are completed.

2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below*after

exiting from self-refresh mode.

Note: tREF (max.) / refresh cycles.

Others

Power-down mode

The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power

consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held

Low. In addition, by setting CKE to High, the SDRAM exits from the power down mode, and command input is

enabled from the next clock. In this mode, internal refresh is not performed.

Clock suspend mode

By driving CKE to Low during a bank active or read/write operation, the SDRAM enters clock suspend mode. During

clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven

High, the SDRAM terminates clock suspend mode, and command input is enabled from the next clock. For details,

refer to the "CKE Truth Table".

Preliminary Data Sheet E0250E10 (Ver. 1.0)

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