EDS5108ABTA-6B View Datasheet(PDF) - Elpida Memory, Inc

Part Name

Description

Manufacturer

EDS5108ABTA-6B

512M bits SDRAM / 54-pin TSOP

Elpida Memory, Inc 

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Bank active command interval

1. Same bank: The interval between the two bank active commands must be no less than tRC.

2. In the case of different bank active commands: The interval between the two bank active commands must be no

less than tRRD.

CLK

Command

ACT

ACT

Address

ROW

ROW

BS

Bank 0

Active

tRC

Bank Active to Bank Active for Same Bank

Bank 0

Active

CLK

Command

Address

ACT

ROW:0

ACT

ROW:1

BS

tRRD

Bank 0

Active

Bank 3

Active

Bank Active to Bank Active for Different Bank

Mode register set to Bank active command interval

The interval between setting the mode register and executing a bank active command must be no less than lMRD.

CLK

Command

MRS

ACT

Address

OPCODE

BS & ROW

IMRD

Mode

Register Set

Bank

Active

Mode register set to Bank active command interval

Preliminary Data Sheet E0250E10 (Ver. 1.0)

40

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