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DS90C383 View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
DS90C383 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link—65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link—65 MHz National-Semiconductor
National ->Texas Instruments National-Semiconductor
DS90C383 Datasheet PDF : 20 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
DS90C383SLC SLC64A (FBGA) Package Pin Description — FPD Link
Transmitter (Continued)
By Pin
G7
TxIN21
I
G8
TxIN23
I
H1
TxIN9
I
H2
VCC
P
H3
TxIN11
I
H4
TxIN14
I
H5
TxIN15
I
H6
TxIN18
I
H7
TxIN19
I
H8
TxIN20
I
G : Ground
I : Input
O : Output
P : Power
NC : No Connect
By Pin Type
C7
PLL VCC
P
E1
VCC
P
E6
VCC
P
H2
VCC
P
B8
NC
C2
NC
C3
NC
F2
NC
F3
NC
F6
NC
DS90CF384 MTD56 TSSOP Package Pin Description — FPD Link Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
FPSHIFT OUT
PWR DOWN
VCC
GND
PLL VCC
PLL GND
LVDS VCC
LVDS GND
I/O No.
I
4
I
4
O 28
I
1
I
1
O1
I
1
I
4
I
5
I
1
I
2
I
1
I
3
Description
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
DS90CF384 64 ball FBGA Package Pin Description — FPD Link Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
FPSHIFT OUT
PWR DOWN
VCC
GND
PLL VCC
PLL GND
LVDS VCC
I/O No.
I
4
I
4
O 28
I
1
I
1
O1
I
1
I
4
I
5
I
1
I
2
I
2
Description
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
15
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