OP1177/OP2177/OP4177
Figure 6 is a scope photograph of the output of the OP1177 in
response to a 400 mV pulse. The load capacitance is 2 nF. The
circuit is configured in positive unity gain, the worst-case condition
for stability.
Placing an R-C network, as shown in Figure 8, parallel to the
load capacitance CL will allow the amplifier to drive higher
values of CL without causing oscillation or excessive overshoot.
There is no ringing and overshoot is reduced from 27% to 5%
using the snubber network.
Optimum values for RS and CS are tabulated in Table I for several
capacitive loads up to 200 nF. Values for other capacitive loads
can be determined experimentally.
Table I. Optimum Values for Capacitive Loads
CL (nF)
RS (⍀)
CS
10
20
0.33 µF
50
30
6.8 nF
200
200
0.47 µF
0
VSY = ؎5V
0
RL = 10k⍀
CL = 2nF
0
0
0
GND0
0
0
0
0
0
0
0 T0IME – 100s/D0IV 0
0
0
0
Figure 6. Capacitive Load Drive without Snubber
0
VSY = ؎5V
0
RL = 10k⍀
RS = 200⍀
0
CL = 2nF
CS = 0.47F
0
0
GND0
0
0
0
0
0
0
0 T0IME – 100s/D0IV 0
0
0
0
Figure 7. Capacitive Load Drive with Snubber
+
400mV ؊
V؊
24
1
3
7 OP1177
V+
VOUT
RS
CL
CS
Figure 8. Snubber Network Configuration
CAUTION: The snubber technique cannot recover the loss of
bandwidth induced by large capacitive loads.
Stray Input Capacitance Compensation
The effective input capacitance in an op amp circuit, Ct, con-
sists of three components. These are: the internal differential
capacitance between the input terminals, the internal common
mode capacitance of each input to ground, and the external
capacitance including parasitic capacitance. In the circuit of
Figure 9, the closed-loop gain increases as the signal frequency
increases.
The transfer function of the circuit is:
1+
R2
R1
(1 +
sCt
R1)
indicating a zero at:
( ) s = R 2 + R1 =
1
R 2R1Ct 2π R1// R 2 Ct
Depending on the value of R1 and R2, the cutoff frequency of the
closed-loop gain may be well below the crossover frequency. In
this case, the phase margin, Φm, can be severely degraded resulting
in excessive ringing or even oscillation.
A simple way to overcome this problem is to insert a capacitor in
the feedback path as shown in Figure 10.
The resulting pole can be positioned to adjust the phase margin.
Setting Cf = (R1/R2)Ct, achieves a phase margin of 90°.
R1
R2
+
V1
–
Ct
V؊
24
1
3
7 OP1177
V+
VOUT
Figure 9. Stray Input Capacitance
Cf
R1
R2
+
V1
–
Ct
V؊
24
1
3
7
V+ OP1177
VOUT
Figure 10. Compensation Using Feedback Capacitor
–12–
REV. B