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DM74AS74 Ver la hoja de datos (PDF) - Fairchild Semiconductor

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DM74AS74 Dual D-Type Positive-Edge-Triggered Flip-Flop with Preset and Clear Fairchild
Fairchild Semiconductor Fairchild
DM74AS74 Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
Switching Characteristics
over recommended operating free air temperature range
Symbol
Parameter
Conditions
fMAX
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
VCC = 4.5V to 5.5V
RL = 500
CL = 50 pF
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
From
Preset
or Clear
Preset
or Clear
Clock
Clock
To
Min
Max
Units
105
MHz
Q or
3
Q
7.5
ns
Q or
3.5
10.5
ns
Q
Q or
3.5
8
ns
Q
Q or
4.5
9
ns
Q
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