DAC8420ESZ-REEL2 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
DAC8420ESZ-REEL2 Datasheet PDF : 24 Pages
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DAC8420
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD 1
16 CLSEL
VOUTD 2
15 CLR
VOUTC 3 DAC8420 14 LD
VREFLO 4 TOP VIEW 13 NC
VREFHI 5 (Not to Scale) 12 CS
VOUTB 6
11 CLK
VOUTA 7
10 SDI
VSS 8
9 GND
NC = NO CONNECT
Figure 4. PDIP and CERDIP
VDD 1
16 CLSEL
VOUTD 2
15 CLR
VOUTC 3 DAC8420 14 LD
VREFLO 4 TOP VIEW 13 NC
VREFHI 5 (Not to Scale) 12 CS
VOUTB 6
11 CLK
VOUTA 7
10 SDI
VSS 8
9 GND
NC = NO CONNECT
Figure 5. SOIC
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
1
VDD
4
VREFLO
5
VREFHI
7, 6, 3, 2
8
9
10
VOUTA through VOUTD
VSS
GND
SDI
11
CLK
12
CS
13
NC
14
LD
15
CLR
16
CLSEL
Description
Positive Power Supply, 5 V to 15 V.
Reference Input. Lower DAC ladder reference voltage input, equal to zero-scale output. Allowable
range is VSS to (VVREFHI − 2.5 V).
Reference Input. Upper DAC ladder reference voltage input. Allowable range is (VDD − 2.5 V) to
(VVREFLO + 2.5 V).
Buffered DAC Analog Voltage Outputs.
Negative Power Supply, 0 V to −15 V.
Power Supply, Digital Ground.
Serial Data Input. Data presented to this pin is loaded into the internal serial-parallel shift register,
which shifts data in, beginning with DAC Address Bit A1. This input is ignored when CS is high. SDI
is CMOS/TTL compatible. The format of the 16-bit serial word is shown in Table 8.
System Serial Data Clock Input, TTL/CMOS Levels. Data presented to the input SDI is shifted into
the internal serial-parallel input register on the rising edge of clock. This input is logically OR’ed
with CS.
Control Input, Device Chip Select, Active Low. This input is logically OR’ed with the clock and
disables the serial data register input when high. When low, data input clocking is enabled (see
Table 6). CS is CMOS/TTL compatible.
No Connect = Don’t Care.
Control Input, Asynchronous DAC Register Load Control, Active Low. The data currently contained
in the serial input shift register is shifted out to the DAC data registers on the falling edge of LD,
independent of CS. Input data must remain stable while LD is low. LD is CMOS/TTL compatible.
Control Input, Asynchronous Clear, Active Low. Sets internal data Register A through Register D to
zero or midscale, depending on current state of CLSEL. The data in the serial input shift register is
unaffected by this control. CLR is CMOS/TTL compatible.
Control Input, Determines action of CLR. If high, a clear command sets the internal DAC Register A
through Register D to midscale (0x800). If low, the registers are set to zero (0x000). CLSEL is CMOS/
TTL compatible.
Rev. B | Page 8 of 24
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