SLAS352C − DECEMBER 2001 − REVISED AUGUST 2004
digital inputs (continued)
Figure 4 shows a schematic of the equivalent CMOS/TTL-compatible digital inputs of the DAC5675, valid for
pins SLEEP and DLLOFF.
Figure 4. CMOS/TTL Digital Equivalent Input
clock input and timing
The DAC5675 comprises a delay locked loop DLL for internal clock alignment. Enabling the DLL is controlled
by pin DLLOFF. The DLL should be enabled for update rates in excess of 100 MSPS. The DLL works only to
maximize setup and hold times of the digital input and does not affect the analog output of the DAC. Figure 5
shows the clock and data input timing diagram. The DAC5675 features a differential clock input. Internal
edge-triggered flip-flops latch the input word on the rising edge of the positive clock input CLK (falling edge of
the negative/complementary clock input CLKC). The DAC core is updated with the data word on the following
rising edge of the positive clock input CLK (falling edge of CLKC). This results in a conversion latency of one
clock cycle. The DAC5675 provides for minimum setup and hold times (>0.25 ns), allowing for noncritical
external interface timing. The clock duty cycle can be chosen arbitrarily under the timing constraints listed in
the electrical characteristics section. However, a 50% duty cycle gives the optimum dynamic performance.
The DAC5675 clock input can be driven by a differential sine wave. The ac coupling, in combination with internal
biasing ensures that the sine wave input is centered at the optimum common-mode voltage that is required for
the internal clock buffer. The DAC5675 clock input can also be driven single-ended, this is shown in Figure 6.
The best SFDR performance is typically achieved by driving the inputs differentially.