Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

DAC5675 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC5675 14-BIT, 400-MSPS DIGITAL-TO-ANALOG CONVERTER TI
Texas Instruments TI
DAC5675 Datasheet PDF : 31 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
DAC5675
SLAS352C − DECEMBER 2001 − REVISED AUGUST 2004
analog current outputs (continued)
Figure 13(a) shows the typical differential output configuration with two external matched resistor loads. The
nominal resistor load of 25 gives a differential output swing of 1 VPP (0.5-VPP single-ended) when applying
a 20-mA full-scale output current. The output impedance of the DAC5675 slightly depends on the output voltage
at nodes IOUT1 and IOUT2. Consequently, for optimum dc-integral nonlinearity, the configuration of
Figure 13(b) should be chosen. In this current/voltage (I-V) configuration, terminal IOUT1 is kept at AVDD by
the inverting operational amplifier. The complementary output should be connected to AVDD to provide a
dc-current path for the current sources switched to IOUT1. The amplifier’s maximum output swing and the DACs
full-scale output current determine the value of the feedback resistor (RFB). The capacitor (CFB) filters the steep
edges of the DAC5675 current output, thereby reducing the operational amplifier’s slew-rate requirements. In
this configuration, the op amp should operate at a supply voltage higher than the resistors output reference
voltage AVDD due to its positive and negative output swing around AVDD. Node IOUT1 should be selected if
a single-ended unipolar output is desired.
3.3 V
Cfb
(AVDD)
DAC5675
25
DAC5675
200
IOUT1
VOUT1
IOUT1
IOUT2
VOUT2
IOUT2
VOUT
+
25
3.3 V
(AVDD)
Optional, For
Single-Ended
Output Referred
to AVDD
3.3 V
(AVDD)
(a) Unbuffered Differential and
Single-Ended Resistor and Buffered
(b) Buffered Single-Ended Output Configuration
Figure 13. Output Configurations
sleep mode
The DAC5675 features a power-down mode that turns off the output current and reduces the supply current
to approximately 45 mA. The power-down mode is activated by applying a logic level 1 to the SLEEP pin (e.g.,
by connecting the SLEEP pin to the AVDD pin). The SLEEP pin must be connected. Power-up and power-down
activation times depend on the value of the external capacitor at node SLEEP. For a nominal capacitor value
of 0.1-µF, powerdown takes less than 5 µs and approximately 3 ms to power back up.
www.ti.com
13
Direct download click here

 

Share Link : 
All Rights Reserved© datasheetq.com 2015 - 2019  ] [ Privacy Policy ] [ Request Datasheet  ] [ Contact Us ]