DAC1003D160HW View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
DAC1003D160HW Datasheet PDF : 19 Pages
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NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
Table 5. Characteristics …continued
VCCD = VCCA = 3.0 V to 3.6 V; AGND and DGND connected together; Tamb = −40 °C to +85 °C; typical values measured at
VCCD = VCCA = 3.3 V, IO(fs) = 20 mA and Tamb = 25 °C; dynamic parameters measured using output schematic given in
Figure 10; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
ICCA
analog supply current
Ptot
total power dissipation
Clock inputs (CLK and CLKN)
fclk = 80 MHz;
fIOUT = fQOUT = 5 MHz
-
73
85
mA
-
422
540
mW
VI(cm)
common-mode input
voltage
-
1.65 -
V
Vi(dif)(p-p) peak-to-peak differential
input voltage
-
1.0
-
V
Analog outputs (IOUT, IOUTN, QOUT and QOUTN)
IO(fs)
full-scale output current differential outputs
Ro
output resistance
Co
output capacitance
Digital inputs (I0 to I9, Q0 to Q9 and GAPD)
4
[1] -
[1] -
-
20
mA
150
-
kΩ
3
-
pF
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
IIL
LOW-level input current
IIH
HIGH-level input current
Reference voltage output (GAPOUT)
VIL = 0.3 VCCD
VIH = 0.7 VCCD
DGND -
0.7 VCCD -
-
5
-
5
0.3 VCCD V
VCCD
V
-
µA
-
µA
VGAPOUT
IGAPOUT
∆VGAPOUT
voltage on pin GAPOUT
current on pin GAPOUT
voltage variation on pin
GAPOUT
external voltage
-
1.31 -
V
-
1
-
µA
-
±133 -
ppm/°C
Clock timing inputs (CLK and CLKN)
fclk
clock frequency
tw(clk)H
HIGH clock pulse width
tw(clk)L
LOW clock pulse width
Input timing (I0 to I9 and Q0 to Q9); see Figure 5
-
80
MHz
5
-
-
ns
5
-
-
ns
th(i)
input hold time
tsu(i)
input set-up time
Output timing (IOUT, IOUTN, QOUT, QOUTN)
1.1
-
−1.5
-
3.4
ns
+0.7
ns
ts
settling time
to ± 0.5 LSB
[1] -
16
-
ns
Digital filter specification (FIR); order N = 42 see Figure 6 and 7 and Table 7
fdata
data rate
-
-
80
MHz
αripple(pb) pass-band ripple
fdata/fclk; 0.005 dB attenuation
-
0.405 -
Bp
power bandwidth
fdata/fclk; 3 dB attenuation
-
0.479 -
αstpb
stop-band attenuation
fdata/fclk = 0.6 dB to 1 dB
-
69
-
dB
td(grp)
group delay time
-
11 Tclk -
ns
Analog signal processing
INL
integral non-linearity
-
±0.2 -
LSB
DNL
differential non-linearity
-
±0.1 -
LSB
DAC1003D160_2
Product data sheet
Rev. 02 — 13 August 2008
© NXP B.V. 2008. All rights reserved.
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