DatasheetQ Logo
Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

TSA5522M View Datasheet(PDF) - Philips Electronics

Part Name
Description
Manufacturer
TSA5522M
Philips
Philips Electronics Philips
TSA5522M Datasheet PDF : 20 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Philips Semiconductors
1.4 GHz I2C-bus controlled synthesizer
Product specification
TSA5522
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
VCC1
VCC2
ICC1
ICC2
fRF
Vi(RF)
fxtal
Io(PNP)
Io(NPN)
Tamb
Tstg
supply voltage (+5 V)
band switch supply voltage (+12 V)
supply current
band switch supply current
note 1
RF input frequency
RF input voltage
fi = 80 to 150 MHz
crystal oscillator input frequency
fi = 150 to 1000 MHz
fi = 1000 to 1400 MHz
PNP band switch buffers output current
NPN open-collector output current
operating ambient temperature
storage temperature (IC)
Note
1. One band switch buffer ON; Io = 20 mA.
MIN.
4.5
VCC1
64
25
28
26
20
40
TYP.
12
22
27
4
20
20
MAX. UNIT
5.5
V
13.5 V
30
mA
32
mA
1 400
3
3
3
25
25
+85
+150
MHz
dBm
dBm
dBm
MHz
mA
mA
°C
°C
GENERAL DESCRIPTION (see Fig.1)
The device is a single chip PLL frequency synthesizer
designed for TV and VCR tuning systems. The circuit
consists of a divide-by-eight prescaler with its own
preamplifier, a 15-bit programmable divider, a crystal
oscillator and its programmable reference divider and a
phase/frequency detector combined with a charge-pump
which drives the tuning amplifier, including 33 V output.
Three high-current PNP band switch buffers are provided
for band switching together with four open-collector NPN
outputs (only one open-collector output on 16-pin
devices). These ports can also be used as input ports [one
Analog-to Digital Converter (ADC) and three general
purpose I/O ports (not available on 16-pin devices)]. An
output is provided to control a Philips mixer/oscillator IC in
combination with the PNP buffers state.
Depending on the reference divider ratio (512, 640
or 1024), the phase comparator operates at 3.90625 kHz,
6.25 kHz or 7.8125 kHz with a 4 MHz crystal. The LOCK
detector bit FL is set to logic 1 when the loop is locked and
is read on the SDA line (status byte) during a read
operation.
The ADC is available for digital AFC control. The ADC
code is read during a read operation on the I2C-bus. The
ADC input is combined with the port P6. In the TEST
mode, this port is also used as a TEST output for fref and
12fdiv (see Table 4).
I2C-bus format
Five serial bytes (including address byte) are required to
address the device, select the VCO frequency, program
the ports, set the charge-pump current and the reference
divider ratio. The device has three independent I2C-bus
addresses selected by applying a specific voltage on AS
input (see Table 3). The general address C2 is always
valid.
1996 Jan 23
3
 

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]