CY7C1354A
CY7C1356A
Switching Waveforms (continued)
Read/Write Timing[42, 45, 47, 48]
CLK
tKC
tKH
tKL
tS
tH
CCKEEN#
tS
tH
RW/WEN#
tS
tH
ADDRESS A1
A2
A3
A4
A5
A6
A7
A8
A9
BWBaW#,aB, W BWb#b,
BWc, BWd
CCEE#
tS
tH
BW(A2)
tS
tH
BW(A4)
BW(A5)
tS
tH
AADDVV//LLDD#
OOEE#
DATA Out (Q)
tKQ
tKQHZ
Q(A1)
tKQLZ
Q(A3)
tKQX
Q(A6)
DATA In (D)
Read
Write
Read
D(A2)
D(A4)
Write
Read
D(A5)
Note:
48. Q(A1) represents the first output from the external address A1. D(A2) represents the input data to the SRAM corresponding to address A2.
Q(A7)
Document #: 38-05161Rev. *E
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