M36DR432AD View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M36DR432AD

32 Mbit (2Mb x16, Dual Bank, Page) Flash Memory and 4 Mbit (256Kb x16) SRAM, Multiple Memory Product

STMicroelectronics 

M36DR432AD, M36DR432BD

SIGNAL DESCRIPTIONS

See Figure 2 Logic Diagram and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A17). Addresses A0-A17

are common inputs for the Flash and the SRAM

components. The Address Inputs select the cells

in the memory array to access during Bus Read

operations. During Bus Write operations they con-

trol the commands sent to the Command Interface

of the internal state machine. During a write oper-

ation, the address inputs for the Flash memory are

latched on the falling edge of the Flash Chip En-

able (EF) or Write Enable (WF), whichever occurs

last, whereas for the SRAM array they are latched

on the falling edge of the SRAM Chip Enable lines

(E1S or E2S) or Write Enable (WS). In the rest of

the datasheet, only the Active Low SRAM Chip

Enable line will be discussed. It will be referred to

as ES.

Address Inputs (A18-A20). Addresses A18-A20

are inputs for the Flash component only. They are

latched during a write operation on the falling edge

of Flash Chip Enable (EF) or Write Enable (WF),

whichever occurs last.

Data Input/Output (DQ0-DQ15). The Data I/O

output the data stored at the selected address dur-

ing a Bus Read operation or input a command or

the data to be programmed during a Write Bus op-

eration.

The input is data to be programmed in the Flash or

SRAM memory array or a command to be written

to the C.I. of the Flash memory. Both are latched

on the rising edge of Flash Write Enable (WF) and,

SRAM Chip Enable lines (ES) or Write Enable

(WS). The output is data from the Flash memory

array or SRAM array, the Electronic Signature

Manufacturer or Device codes, the Block Protec-

tion status, the Configuration Register status or

the Status Register Data (Polling bit DQ7, Toggle

bits DQ6 and DQ2, Error bit DQ5 or Erase Timer

bit DQ3) depending on the address. Outputs are

valid when Flash Chip Enable (EF) and Output En-

able (GF) or SRAM Chip Enable lines (ES) and

Output Enable (GS) are active.

The output is high impedance when both the Flash

chip and the SRAM chip are deselected or the out-

puts are disabled and when Reset (RPF) is at VIL.

Flash Chip Enable (EF). The Chip Enable input

activates the Flash memory control logic, input

buffers, decoders and sense amplifiers. When

Chip Enable is at VIH the memory is deselected

and the power consumption is reduced to the

standby level.

Flash Output Enable (GF). gates the outputs

through the data buffers during a read operation.

When Output Enable, GF, is at VIH the outputs are

High impedance.

Flash Write Enable (WF). The Write Enable

controls the Bus Write operation of the Flash

memory’s Command Interface.

Flash Write Protect (WPF). Write Protect is an

input that gives an additional hardware protection

for each Flash block. When Write Protect is at VIL,

the locked-down blocks cannot be locked or un-

locked. When Write Protect is at VIH, the Lock-

Down is disabled and the Locked-Down blocks

can be locked or unlocked. Refer to Table 8, Read

Protection Register.

Flash Reset/Power-Down (RPF). The Reset/

Power-Down input provides hardware reset of the

Flash memory, and/or Power-Down functions, de-

pending on the Flash Configuration Register sta-

tus. Reset or Power-Down of the memory is

achieved by pulling RPF to VIL for at least tPLPH.

The Reset/Power-Down function is set in the Con-

figuration Register (see Set Configuration Regis-

ter Command). If it is set to ‘0’ the Reset function

is enabled, if it is set to ‘1’ the Power-Down func-

tion is enabled. After a Reset or Power-Up the

power save function is disabled and all blocks are

locked.

The memory Command Interface is reset on Pow-

er Up to Read Array. Either Chip Enable or Write

Enable must be tied to VIH during Power Up to al-

low maximum security and the possibility to write a

command on the first rising edge of Write Enable.

After a Reset, when the device is in Read, Erase

Suspend Read or Standby, valid data will be out-

put tPHQ7V1 after the rising edge of RPF. If the de-

vice is in Erase or Program, the operation will be

aborted and the reset recovery will take a maxi-

mum of tPLQ7V. The memory will recover from Re-

set/Power-Down tPHQ7V2 after the rising edge of

RPF. See Tables 18 and 19, and Figure 12.

VDDF Supply Voltage (1.65V to 2.2V). VDDF pro-

vides the power supply to the internal core and I/O

pins of the memory device. It is the main power

supply for all operations (read, program and

erase).

VPPF Programming Voltage (11.4V to 12.6V).

VPPF provides a high voltage power supply for fast

factory programming. VPPF is required to use the

Double Word and Quadruple Word Program com-

mands.

VSSF Ground. VSSF ground is the reference for

the core supply. It must be connected to the sys-

tem ground.

SRAM Chip Enable (ES). The Chip Enable in-

puts for SRAM activate the memory control logic,

input buffers and decoders. ES at VIH deselects

8/52

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