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M36DR432AD View Datasheet(PDF) - STMicroelectronics

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Description
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M36DR432AD Datasheet PDF : 52 Pages
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M36DR432AD, M36DR432BD
Table 2. Main Operation Modes
Operation Mode
EF GF WF RPF WPF ES GS WS UBS, LBS(1) DQ15-DQ0
Read
VIL VIL VIH VIH
VIH
SRAM must be disabled
Data Output
Page Read
VIL VIL VIH VIH
VIH
SRAM must be disabled
Data Output
Write
VIL VIH VIL VIH
VIH
SRAM must be disabled
Data Input
Standby
VIH X
X
VIH
VIH
Any SRAM mode is allowed
Hi-Z
Reset/
Power-Down
X
X
X
VIL
VIH
Any SRAM mode is allowed
Hi-Z
Output Disable
VIL VIH VIH VIH
VIH
Any SRAM mode is allowed
Hi-Z
Read
Flash must be disabled
VIL VIL VIH
VIL
Data out
Word Read
Write
Flash must be disabled
VIL VIH VIL
VIL
Data in Word
Write
Standby/Power
Down
Any Flash mode is allowable
VIH
X
X
X
XX
X
VIH
Hi-Z
Hi-Z
VIH
X
X
X
Hi-Z
Data Retention
Any Flash mode is allowable
X
XX
VIH
Hi-Z
Output Disable
Any Flash mode is allowable
VIL VIH VIH
X
Note: 1. X = Don’t care (VIL or VIH).
2. If UBS and LBS are tied together the bus is at 16 bit. For an 8 bit bus configuration use UBS and LBS separately.
Hi-Z
11/52
 

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