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TSA5521M/C4 データシートの表示(PDF) - Philips Electronics

部品番号TSA5521M/C4 Philips
Philips Electronics Philips
コンポーネント説明1.3 GHz universal bus-controlled TV synthesizer; 3-wire


TSA5521M/C4 Datasheet PDF : 24 Pages
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Philips Semiconductors
1.3 GHz universal bus-controlled
TV synthesizer
Product specification
TSA5520; TSA5521
3-wire bus mode (SW = open-circuit or VCC1);
see Figs 3, 4 and 5
During a HIGH level on the CE input, the data is clocked
into the data register at the HIGH-to-LOW transition of the
clock pulse. The first four bits control the band switch
buffers and are loaded into the internal band switch
register on the 5th rising edge of the clock pulse.
The frequency bits are loaded into the frequency register
at the HIGH-to-LOW transition of the chip enable line when
an 18-bit or 19-bit data word is transmitted.
At power-on the charge-pump current is set to 280 µA, the
tuning voltage output is disabled (Vtune = 33 V in
application; see Fig.12), the test bits T2, T1 and T0 are set
to the normal mode and RSB is set to 1 (TSA5520) or 0
(TSA5521). When an 18-bit data word is transmitted, the
most significant bit of the divider N14 is internally set to 0
and bit RSA is set to 1. When a 19-bit data word is
transmitted, bit RSA is set to 0.
When a 27-bit word is transmitted, the frequency bits are
loaded into the frequency register on the 20th rising edge
of the clock pulse and the control bits at the HIGH-to-LOW
transition of the chip enable line. In this mode, the
reference divider is given by the RSA and RSB bits (see
Table 7). The test bits T2, T1 and T0, the charge-pump
bit CP, the ratio select bit RSB and the OS bit can only be
selected or changed with a 27-bit transmission. They
remain programmed if an 18-bit or a 19-bit transmission
occurs. Only RSA is controlled by the transmission length
when the 18-bit or 19-bit format is used.
A data word of less than 18 bits will not affect the
frequency register of the device. The definition of the bits
is unchanged compared to the I2C bus mode.
The power-on detection threshold voltage VPOR is fixed to
VCC1 = 2 V at room temperature. Below this threshold, the
device is reset to the power-on state described above.
Table 6 Test bits
T2 T1 T0
DEVICE OPERATION
0 0 1 normal mode
0 1 X charge-pump is OFF
1 1 0 charge-pump is sinking current
1 1 1 charge-pump is sourcing current
1 0 0 fref is available at LOCK output
1 0 1 12fdiv is available at LOCK output
Table 7 Ratio select bits
RSA
X
0
1
RSB
0
1
1
REFERENCE DIVIDER
640
1 024
512
For TSA5520 bit RSB = 1 at power-on; the reference divider is 512 or 1024.
For TSA5521 bit RSB = 0 at power-on; the reference divider is 640.
For TSA5520/TSA5521 the value of RSB can also be programmed by using the 27-bit data format. When returning to the normal mode, bit RSB remains
as programmed with the 27-bit data word.
Fig.3 Normal mode; 18-bit data format (RSA = 1).
1996 Oct 10
8
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The device is a single-chip PLL frequency synthesizer designed for TV and VCR tuning systems.

The circuit consists of a divide-by-eight prescaler with its own preamplifier, a 15-bit programmable divider, a crystal oscillator and its programmable reference divider and a phase/frequency detector combined with a charge-pump which drives the tuning amplifier and the 33 V output.

Four high-current PNP band switch buffers are provided for band switching. Two PNP buffers can be switched on simultaneously. The sum of the collector currents is limited to 50 mA.

 

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