C8051F011 View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
C8051F011 Datasheet PDF : 170 Pages
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C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
PRELIMINARY
Figure 1.1. C8051F000/05/10/15 Block Diagram
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AGND
AGND
TCK
TMS
TDI
TDO
/RST
XTAL1
XTAL2
Digital Power
Analog Power
JTAG Boundary Scan
Logic
Debug HW
8
0
5 Reset
32kbyte
FLASH
256 byte
RAM
VDD
Monitor,
WDT
1
2048 byte
XRAM
(F005/15 only)
C
External
Oscillator
Circuit
o
r System Clock
SFR Bus
Internal
e
Oscillator
Clock & Reset
Configuration
Port I/O
Config.
UART
SMBus
SPI Bus
PCA
Timers
0,1,2
Timer 3
Port 0
Latch
Port 1
Latch
Port 2
Latch
Crossbar
Config.
Port 3
Latch
Analog
Interface
Config. &
Control
P
C
0
R
O
D
r
S
v
S
B
A
P
1
R
D
r
S
v
W
P
I
2
T
C
H
D
r
v
P
3
D
r
v
ADC
100ksps
A
Prog
Gain
M
U
X
TEMP
VREF
DAC0
(12-Bit)
DAC1
(12-Bit)
CP0
CP1
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
VREF
DAC0
DAC1
CP0+
CP0-
CP1+
CP1-
4.2001; Rev. 1.3
CYGNAL Integrated Products, Inc. 2001
Page 9
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