C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
PRELIMINARY
Figure 5.6. ADC0CF: ADC Configuration Register (C8051F00x)
R/W
R/W
R/W
R/W
ADCSC2 ADCSC1 ADCSC0
-
Bit7
Bit6
Bit5
Bit4
R/W
R/W
-
AMPGN2
Bit3
Bit2
Bits7-5: ADCSC2-0: ADC SAR Conversion Clock Period Bits
000: SAR Conversion Clock = 1 System Clock
001: SAR Conversion Clock = 2 System Clocks
010: SAR Conversion Clock = 4 System Clocks
011: SAR Conversion Clock = 8 System Clocks
1xx: SAR Conversion Clock = 16 Systems Clocks
(Note: the SAR Conversion Clock should be ≤ 2MHz)
Bits4-3: UNUSED. Read = 00b; Write = don’t care
Bits2-0: AMPGN2-0: ADC Internal Amplifier Gain
000: Gain = 1
001: Gain = 2
010: Gain = 4
011: Gain = 8
10x: Gain = 16
11x: Gain = 0.5
R/W
AMPGN1
Bit1
R/W
AMPGN0
Bit0
Reset Value
01100000
SFR Address:
0xBC
4.2001; Rev. 1.3
CYGNAL Integrated Products, Inc. 2001
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