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DS90CR287MTD_04 データシートの表示(PDF) - National ->Texas Instruments

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DS90CR287MTD_04 +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHz National-Semiconductor
National ->Texas Instruments National-Semiconductor
DS90CR287MTD_04 Datasheet PDF : 16 Pages
First Prev 11 12 13 14 15 16
Applications Information (Continued)
ramic type in surface mount form factor) between each VCC
and the ground plane(s) are recommended. The three ca-
pacitor values are 0.1 µF, 0.01 µF and 0.001 µF. An example
is shown in Figure 18. The designer should employ wide
traces for power and ground and ensure each capacitor has
its own via to the ground plane. If board space is limiting the
number of bypass capacitors, the PLL VCC should receive
the most filtering/bypassing. Next would be the LVDS VCC
pins and finally the logic VCC pins.
FIGURE 17. LVDS Serialized Link Termination
10108724
10108725
FIGURE 18. CHANNEL LINK
Decoupling Configuration
CLOCK JITTER: The CHANNEL LINK devices employ a
PLL to generate and recover the clock transmitted across the
LVDS interface. The width of each bit in the serialized LVDS
data stream is one-seventh the clock period. For example, a
85 MHz clock has a period of 11.76 ns which results in a data
bit width of 1.68 ns. Differential skew (t within one differen-
tial pair), interconnect skew (t of one differential pair to
another) and clock jitter will all reduce the available window
for sampling the LVDS serial data streams. Care must be
taken to ensure that the clock input to the transmitter be a
clean low noise signal. Individual bypassing of each VCC to
ground will minimize the noise passed on to the PLL, thus
creating a low jitter LVDS clock. These measures provide
more margin for channel-to-channel skew and interconnect
skew as a part of the overall jitter/skew budget.
INPUT CLOCK: The input clock should be present at all
times when the part in enabled. If the clock is stopped, the
PWR DOWN pin should be asserted to disable the PLL.
Once the clock is active again, the part can then be enabled.
Do not enable the part without a clock present.
COMMON-MODE vs. DIFFERENTIAL MODE NOISE MAR-
GIN: The typical signal swing for LVDS is 300 mV centered
at +1.2V. The CHANNEL LINK receiver supports a 100 mV
threshold therefore providing approximately 200 mV of dif-
ferential noise margin. Common-mode protection is of more
importance to the system’s operation due to the differential
data transmission. LVDS supports an input voltage range of
Ground to +2.4V. This allows for a ±1.0V shifting of the
center point due to ground potential differences and
common-mode noise.
TRANSMITTER INPUT CLOCK: The transmitter input clock
must always be present when the device is enabled (PWR
DOWN = HIGH). If the clock is stopped, the PWR DOWN pin
must be used to disable the PLL. The PWR DOWN pin must
be held low until after the input clock signal has been reap-
plied. This will ensure a proper device reset and PLL lock to
occur.
POWER SEQUENCING AND POWERDOWN MODE: Out-
puts of the CHANNEL LINK transmitter remain in TRI-STATE
until the power supply reaches 2V. Clock and data outputs
will begin to toggle 10 ms after VCC has reached 3V and the
Powerdown pin is above 1.5V. Either device may be placed
into a powerdown mode at any time by asserting the Pow-
erdown pin (active low). Total power dissipation for each
device will decrease to 5 µW (typical).
The transmitter input clock may be applied prior to powering
up and enabling the transmitter. The transmitter input clock
may also be applied after power up; however, the use of the
PWR DOWN pin is required as described in the Transmitter
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