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DS90CR287MTD_04 データシートの表示(PDF) - National ->Texas Instruments

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DS90CR287MTD_04 +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHz National-Semiconductor
National ->Texas Instruments National-Semiconductor
DS90CR287MTD_04 Datasheet PDF : 16 Pages
First Prev 11 12 13 14 15 16
AC Timing Diagrams (Continued)
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)(Note 7) + ISI (Inter-symbol interference)(Note 8)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 7: Cycle-to-cycle jitter is less than 150ps at 85MHz.
Note 8: ISI is dependent on interconnect length; may be zero
FIGURE 16. Receiver LVDS Input Skew Margin
10108720
DS90CR287 MTD56 (TSSOP) Package Pin Description — Channel Link
Transmitter
Pin Name
TxIN
TxOUT+
TxOUT−
TxCLK IN
TxCLK OUT+
TxCLK OUT−
PWR DOWN
VCC
GND
PLL VCC
PLL GND
LVDS VCC
LVDS GND
I/O No.
Description
I
28 TTL level input.
O
4 Positive LVDS differential data output.
O
4 Negative LVDS differential data output.
I
1 TTL level clock input. The rising edge acts as data strobe. Pin name TxCLK IN. See
Applications Information section.
O
1 Positive LVDS differential clock output.
O
1 Negative LVDS differential clock output.
I
1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at
power down. See Applications Information section.
I
4 Power supply pins for TTL inputs.
I
5 Ground pins for TTL inputs.
I
1 Power supply pin for PLL.
I
2 Ground pins for PLL.
I
1 Power supply pin for LVDS outputs.
I
3 Ground pins for LVDS outputs.
DS90CR288A MTD56 (TSSOP) Package Pin Description — Channel Link
Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
VCC
I/O No.
Description
I
4 Positive LVDS differential data inputs.
I
4 Negative LVDS differential data inputs.
O 28 TTL level data outputs.
I
1 Positive LVDS differential clock input.
I
1 Negative LVDS differential clock input.
O
1 TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
I
1 TTL level input. When asserted (low input) the receiver outputs are low.
I
4 Power supply pins for TTL outputs.
11
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