BU4209FVE View Datasheet(PDF) - ROHM Semiconductor
Part Name
Description
Manufacturer
BU4209FVE Datasheet PDF : 16 Pages
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BU42xx series BU43xx series
Datasheet
●Application Information
Explanation of Operation
For both the open drain type (Fig.15) and the CMOS output type (Fig.16), the detection and release voltages are used as
threshold voltages. When the voltage applied to the VDD pins reaches the applicable threshold voltage, the VouT terminal
voltage switches from either “High” to “Low” or from “Low” to “High”. BU42xx and BU43xx series have delay time function
which set tPLH (Output “Low” ”High”) using an external capacitor (CCT). Because the BU42xx series uses an open drain
output type, it is necessary to connect a pull-up resistor to VDD or another power supply if needed [The output “High”
voltage (VOUT) in this case becomes VDD or the voltage of the other power supply].
VDD
R1
Vref
R2
Q3
R3
GND
VDD
VOUT
RESET
Q1
CT
Fig.15 (BU42xx series Internal Block Diagram)
VDD
GND
R1
Vref
R2
R3
VDD
Q3
Q2
RESET
VOUT
Q1
CT
Fig.16 (BU43xx type Internal Block Diagram)
Setting of Detector Delay Time
The delay time of this detector IC can be set at the rise of VDD by the capacitor connected to CT terminal.
Delay time at the rise of VDD tPLH:Time until when VouT rises to 1/2 of VDD after VDD rises up and beyond the release
voltage(VDET+∆VDET)
CCT:
RCT:
TPLH=-1×CCT×RCT×ln
VDD-VCTH
VDD
CT pin Externally Attached Capacitance
CT pin Internal Impedance(P.3 RCT refer.)
VCTH:
ln:
CT pin Threshold Voltage(P.3 VCTH refer.)
Natural Logarithm
Reference Data of Falling Time (tPHL) Output
Examples of Falling Time (tPHL) Output
Part Number
BU4245
tPHL [µs]
275.7
BU4345
359.3
* This data is for reference only.
The figures will vary with the application, so please confirm the actual operating conditions before use.
Timing Waveforms
Example: The following shows the relationship between the input voltage VDD, the CT Terminal Voltage VCT and the output
voltage VOUT when the input power supply voltage VDD is made to sweep up and sweep down (The circuits are shown in
Fig.15 and 16).
① When the power supply is turned on, the output is unstable from
after over the operating limit voltage (VOPL) until tPHL. Therefore, it is
VDET+ΔVDET
VDET
VDD
VOPL
0V
⑤
possible that the reset signal is not outputted when the rise time of
VDD is faster than tPHL.
② When VDD is greater than VOPL but less than the reset release
voltage (VDET+∆VDET), the CT terminal (VCT) and output (VOUT)
VCT
1/2 VDD
voltages will switch to L.
③ If VDD exceeds the reset release voltage (VDET+VDET), then VOUT
switches from L to H (with a delay to the CT terminal).
④ If VDD drops below the detection voltage (VDET) when the power
VOUT
tPHL
tPLH
tPHL
tPLH
supply is powered down or when there is a power supply fluctuation,
VOUT switches to L (with a delay of tPHL).
⑤ The potential difference between the detection voltage and the
①② ③ ④
Fig.17 Timing Waveforms
release voltage is known as the hysteresis width (VDET). The system
is designed such that the output does not toggle with power supply
fluctuations within this hysteresis width, preventing malfunctions due
to noise.
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TSZ22111・15・001
10/13
TSZ02201-0R7R0G300050-1-2
03.Feb.2014 Rev.008
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