BU1924 View Datasheet(PDF) - ROHM Semiconductor
Part Name
Description
Manufacturer
BU1924 Datasheet PDF : 5 Pages
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Audio ICs
BU1924 / BU1924F
!Electrical characteristics (unless otherwise noted, Ta = 25°C, VDD1 = VDD2 = 5.0V, VSS1 = VSS2 = 0.0V)
Parameter
Operating current
Reference voltage
Input current 1
Output current 1
Input current 2
Output current 2
Symbol
IDD
Vref
IIN1
IOUT1
IIN2
IOUT2
Output high level voltage 1 VOH1
Output low level voltage 1
〈Filter block〉
Center frequency
Gain
Attenuation 1
Attenuation 2
Attenuation 3
S / N ratio
Maximum input level
VOL1
FC
GA
ATT1
ATT2
ATT3
SN
VMAX1
Min.
−
−
−
−
−
−
VDD2
−1.0
−
Typ.
4.5
1/2VDD1
−
−
−
−
VDD2
−0.3
0.2
Max.
7.0
−
1.0
1.0
1.0
1.0
−
1.0
Unit
mA
IDD1+IDD2
V Pin 3
µA MUX
µA MUX
µA XI
µA XI
Conditions
VIN=VDD1
VIN=VDD1
VIN=VDD2
VIN=VDD2
V
RCLK RDATA QUAL IO=−1.0mA
V
RCLK RDATA QUAL IO=1.0mA
56.5 57.0 57.5 kHz
20
23
26
dB F=57.0kHz
18
22
−
dB 57kHz±4kHz
65
80
−
dB 38kHz
35
50
−
dB 67kHz
30
40
−
dB 57kHz VIN=3mVrms
−
−
500 mVrms
〈Demodulator〉
RDS detector sensitivity
RDS input level
ARI detector sensitivity
Data rate
Clock transient vs. data
SRDS
MRDS
SARI
DRATE
CT
−
0.5
1.0 mVrms
1.0
−
300 mVrms
−
1.5
3.0 mVrms
− 1187.5 −
Hz
−
4.3
−
µs
Not designed for radiation resistance.
!Output data timing
RCLK
RDATA
T1
T5
T1
T3
T4
T2
T1=T2=4.3µS
T3=T4=421µS
T5=T6=416.7µS
T6
T2
The clock (RCLK) frequency is 1187.5Hz. Depending on the state of the internal PLL clock, the data (RDATA) is replaced
in synchronous with either the rising or falling or falling edge of the clock. To read the data, you may choose either the
rising or falling edge of the clock as the reference. The data is valid for 416.7µs. after the reference clock edge.
QUAL pin operation : Indicates the quality of the demodulated data.
(1) Good data : HI
(2) Poor data : LO
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