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BT8110 View Datasheet(PDF) - Unspecified

Part NameDescriptionManufacturer
BT8110 High-Capacity ADPCM Processor ETC
BT8110 Datasheet PDF : 84 Pages
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2.0 Functional Description
2.3 Direct Framer Interface Operation
High-Capacity ADPCM Processor
2.3.2 E1 Framer Interface
In this configuration, address 0x40 must be set to a value of 0x1C to properly set
the Bt8110/8110B mode. The per-channel control registers given in Table 3-3
must be configured for the appropriate code selection, coding type, and
transparency. The Bt8110 allows only 56 kbit/s data rate in transparent mode. The
Bt8110B operates at a full 64 kbit/s data rate. The full-rate PCM signals are serial
and are connected directly to the SERIAL_IN and SERIAL_OUT pins.
In this application the PSIGEN input must be held low, thus enabling the
parallel interface for the ADPCM inputs PSIG[7:0] and outputs D[7:0]. The
ADPCM inputs and outputs are timed by the signal ADPCM_STB. The input to
each Bt8110 is applied to the parallel input PSIG[7:0] with the most significant
bit at PSIG[7]. The output is obtained from the ROM data bus D[7:0] with the
most significant bit at D[7].
The Bt8110/8110B interfaces to the E1 framer which transmits and receives a
digital line at the 2.048 Mbit/s primary rate. The slip buffer of the E1 framer
frame-synchronizes the receive signal to the transmit signal allowing the
Bt8110/8110B to operate synchronously on both signals.
The ADPCM input data must be valid at the positive edge of ADPCM_STB;
the ADPCM output data is valid at the positive edge. Due to the processing delay
of the Bt8110/8110B, there is a five-channel offset between the timing of the
ADPCM input and PCM output.
The ADPCM output is always 5 bits (for 40 kbit/s coding and for all
embedded codes) or less. The ADPCM input includes up to 5 ADPCM input bits
and 2 bits to indicate the number of bits in the decoder input when embedded
encoding is used. On the Bt8110 only, the input to PSIG[0], the least significant
bit, must be left open or held at a logic low level (this pin has an internal
pull-down resistor).
The required 8.192 MHz clock source should be phased-locked to incoming
PCM data. A complete implementation of a 60-channel E1 speech compression
interface utilizing the Bt8510 E1 Framer and the Bt8110/8110B is detailed in
Appendix C, E1 Speech Compression Interface.
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