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FLINK3V8BT-85 データシートの表示(PDF) - National ->Texas Instruments

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FLINK3V8BT-85 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-85 MHz, +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-85 MHz National-Semiconductor
National ->Texas Instruments National-Semiconductor
FLINK3V8BT-85 Datasheet PDF : 17 Pages
First Prev 11 12 13 14 15 16 17
AC Timing Diagrams (Continued)
FIGURE 16. Timing Diagram of the Input cycle-to-cycle clock jitter
10086828
DS90C385 MTD56 (TSSOP) Package Pin Description —
FPD Link Transmitter
Pin Name
TxIN
TxOUT+
TxOUT−
TxCLKIN
R_FB
TxCLK OUT+
TxCLK OUT−
PWR DOWN
VCC
GND
PLL VCC
PLL GND
LVDS VCC
LVDS GND
I/O No.
I 28
O4
O4
I1
I1
O1
O1
I1
I3
I4
I1
I2
I1
I3
Description
TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differentiaI data output.
Negative LVDS differential data output.
TTL Ievel clock input. Pin name TxCLK IN.
Programmable strobe select (See Table 1).
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down. See Applications Information section.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
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