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DM74S373WM Ver la hoja de datos (PDF) - Fairchild Semiconductor

Número de pieza
componentes Descripción
DM74S373WM Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
August 1986
Revised May 2000
DM74S373 • DM74S374
3-STATE Octal D-Type Transparent Latches
and Edge-Triggered Flip-Flops
General Description
These 8-bit registers feature totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for inter-
face or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight latches of the DM74S373 are transparent D-type
latches meaning that while the enable (G) is HIGH the Q
outputs will follow the data (D) inputs. When the enable is
taken LOW the output will be latched at the level of the
data that was set up.
The eight flip-flops of the DM74S374 are edge-triggered D-
type flip-flops. On the positive transition of the clock, the Q
outputs will be set to the logic states that were set up at the
D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines
simplify system design as ac and dc noise rejection is
improved by typically 400 mV due to the input hysteresis. A
buffered output control input can be used to place the eight
outputs in either a normal logic state (HIGH or LOW logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines signifi-
The output control does not affect the internal operation of
the latches or flip-flops. That is, the old data can be
retained or new data can be entered even while the outputs
are OFF.
s Choice of 8 latches or 8 D-type flip-flops in a single
s 3-STATE bus-driving outputs
s Full parallel-access for loading
s Buffered control inputs
s P-N-P input reduce D-C loading on data lines
Ordering Code:
Order Number Package Number
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
© 2000 Fairchild Semiconductor Corporation DS006486
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