SP706SEN View Datasheet(PDF) - Exar Corporation

Part Name

Description

Manufacturer

SP706SEN

+3.0V/+3.3V low power microprocessor supervisory circuits

Exar Corporation 

SP706R/S/T - SP708R/S/T

3.0V/3.3V Low Power Microprocessor Supervisory

Circuits

FEATURES

The SP706R/S/T and SP708R/S/T series

provides four key functions:

1. A reset output during power-up, power-down

and brownout conditions.

2. An independent watchdog output that goes

LOW if the watchdog input has not been toggled

within 1.6 seconds.

3. A 1.25V threshold detector for power-fail

warning, low battery detection, or monitoring a

power supply other than +3.3V/+3.0V.

4. An active-LOW manual-reset that allows

RESET to be triggered by a pushbutton switch.

The SP706R/S/T devices are the same as the

SP708R/S/T devices except for the active-HIGH

RESET substitution of the watchdog timer.

THEORY OF OPERATION

The SP706R/S/T-SP708R/S/T series is a

microprocessor (µP) supervisory circuit that

monitors the power supplied to digital circuits

such as microprocessors, microcontrollers, or

memory. The series is an ideal solution for

portable, battery-powered equipment that

requires

power

supply

monitoring.

Implementing this series will reduce the

number of components and overall complexity.

The watchdog functions of this product family

will continuously oversee the operational status

of a system. The operational features and

benefits of the SP706R/S/T-SP708R/S/T series

are described in more detail below.

previously initiated reset pulse, the pulse

continues for at least another 140ms. On power

down, once VCC falls below the reset threshold,

RESET stays LOW and is guaranteed to be 0.4V

or less until VCC drops below 1V.

The active-HIGH RESET output is simply the

complement of the RESET output and is

guaranteed to be valid with VCC down to 1.1V.

Some µPs, such as Intel's 80C51, require an

active-HIGH reset pulse.

WATCHDOG TIMER

The SP706R/S/T-SP708R/S/T watchdog circuit

monitors the µP's activity. If the µP does not

toggle the watchdog input (WDI) within 1.6

seconds and WDI is not tri-stated, WDO goes

LOW. As long as RESET is asserted or the WDI

input is tri-stated, the watchdog timer will stay

cleared and will not count. As soon as RESET is

released and WDI is driven HIGH or LOW, the

timer will start counting. Pulses as short as

50ns can be detected.

Typically, WDO will be connected to the non-

maskable interrupt input (NMI) of a µP. When

VCC drops below the reset threshold, WDO will

go LOW whether or not the watchdog timer had

timed out. Normally this would trigger an NMI

but RESET goes LOW simultaneously and thus

overrides the NMI.

If WDI is left unconnected, WDO can be used as

a low-line output. Since floating WDI disables

the internal timer, WDO goes LOW only when

VCC falls below the reset threshold, thus

functioning as a low-line output.

RESET OUTPUT

A microprocessor's reset input starts the µP in

a known state. The SP706R/S/T-SP708R/S/T

series asserts reset during power-up and

prevents code execution errors during power

down or brownout conditions.

On power-up, once VCC reaches 1V, RESET is a

guaranteed logic LOW of 0.4V or less. As VCC

rises, RESET stays LOW. When VCC rises above

the reset threshold, an internal timer releases

RESET after 200ms. RESET pulses LOW

whenever VCC dips below the reset threshold,

such as in a brownout condition. When a

brownout condition occurs in the middle of a

© 2015 Exar Corporation

11/17

Fig. 18: Watchdog Timing Waveforms

Rev. 3.0.0

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