8. Device Addressing
Standard EEPROM Access: The 1K and 2K EEPROM device requires an 8-bit device address word following a Start
condition to enable the chip for a read or write operation.
The device address word consists of a mandatory ‘1010’ (Ah) sequence for the first four most significant bits as shown
in Figure 10-1 on page 12. This is common to all Serial EEPROM devices.
The next three bits are the A2, A1, and A0 device address bits for the 1K and 2K EEPROM. These three bits must
compare to their corresponding hard-wired input pins A2, A1, and A0 in order for the part to acknowledge.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and
a write operation is initiated if this bit is low.
Upon a valid compare of the device address with hard-wired input pins A2, A1, and A0, the EEPROM will output a zero. If
a compare is not successfully made, the chip will return to a standby state.
Serial Number Access: The AT24CS01 and AT24CS02 utilizes a separate memory block containing a factory
programmed 128-bit serial number. Access to this memory location is obtained by beginning the device address word
with a ‘1011’ (Bh) sequence.
The behavior of the next three bits (A2, A1, and A0) remain the same as during a standard EEPROM addressing
sequence. These three bits must compare to their corresponding hard-wired input pins A2, A1, and A0 in order for the part
The eighth bit of the device address needs be set to a one to read the Serial Number. A zero in this bit position, other
than during a dummy write sequence to set the address pointer, will result in a unknown data read from the part. Writing
or altering the 128-bit serial number is not possible.
Further specific protocol is needed to read the serial number from of the device. See Read Operations on page 11 for
more details on accessing the special feature.
9. Write Operations
Byte Write: A Byte Write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first
8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such
as a microcontroller, must terminate the write sequence with a Stop condition. At this time the EEPROM enters an
internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the
EEPROM will not respond until the Write is complete (see Figure 10-2 on page 12).
Page Write: The 1K and 2K EEPROM are capable of an 8-byte Page Write. A Page Write is initiated in the same way as
a Byte Write, but the microcontroller does not send a Stop condition after the first data word is clocked in. Instead, after
the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must terminate the Page Write
sequence with a Stop condition (see Figure 10-3 on page 12).
The data word address lower three bits are internally incremented following the receipt of each data word. The higher
data word address bits are not incremented, retaining the memory page row location. When the internally generated
word address reaches the page boundary, the subsequent byte loaded will be placed at the beginning of the same page.
If more than eight data words are transmitted to the EEPROM, the data word address will roll-over and previously loaded
data will be overwritten.
Acknowledge Polling: Once the internally timed write cycle has started and the EEPROM inputs are disabled,
acknowledge polling can be initiated. This involves sending a Start condition followed by the device address word. The
Read/Write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM
respond with a zero allowing the next read or write sequence to begin.
Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 10