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AS29LV016J View Datasheet(PDF) - Austin Semiconductor

Part NameAS29LV016J AUSTIN
Austin Semiconductor AUSTIN
Description16 Megabit (2M x 8-Bit / 1M x 16-Bit) CMOS 3.0 Volt-Only Boot Sector Flash Memory
AS29LV016J Datasheet PDF : 40 Pages
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COTS PEM
BOOT SECTOR FLASH
Austin Semiconductor, Inc.
AS29LV016J
Table 8: Primary Vendor-Specific Extended Query
Addresses
(Word Mode)
40h
41h
42h
43h
44h
45h
Addresses
(Byte Mode)
80h
82h
84h
86h
88h
8Ah
46h
8Ch
47h
8Eh
48h
90h
49h
92h
4Ah
94h
4Bh
96h
4Ch
98h
4Dh
9Ah
4Eh
9Ch
Data
0050h
0052h
0049h
0031h
0033h
000Ch
0002h
0001h
0001h
0004h
0000h
0000h
0000h
0000h
0000h
Description
Query-unique ASCII string "PRI"
Major version number, ASCII
Major version number, ASCII
Address Sensitive Unlock
0=Required, 1=Not Required
Erase Suspend
0=Not Supported, 1=To Read Only, 2=To Read and Write
Sector Protect
0=Not Supported, X=Number of Sectors Per Group
Sector Temorary Unprotect
00=Not Supported, 01=Supported
Sector Protect / Unprotect Scheme
01=29F040 mode, 02=29F016 mode,
03=29F400 mode, 04=29LV800A mode
Simultaneous Operation
00=Not Supported, 01=Supported
Burst Mode Type
00=Not Supported, 01= Supported
Page Mode Type
00=Not Supported, 01=4 Word Page, 02= 8 Word Page
ACC (Acceleration) Supply Minimum
00=Not Supported, D7-D4: Volt, D3-D0; 100mV
ACC (Acceleration) Supply Minimum
00=Not Supported, D7-D4: Volt, D3-D0; 100mV
HARDWARE DATA PROTECTION
The command sequence requirement of unlock cycles WRITE PULSE GLITCH PROTECTION
for programming or erasing provides data protection against Noise pulses of less than 5 ns (typical) on OE#, CE# or
inadvertent writes (refer to Table 9 on page 21 for command WE# do not initiate a write cycle.
definitions). In addition, the following hardware data
protection measures prevent accidental erasure or LOGICAL INHIBIT
programming, which might otherwise be caused by Write cycles are inhibited by holding any one of OE# =
spurious system level signals during VCC power-up and VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
power-down transitions, or from system noise.
CE# and WE# must be a logical zero while OE# is a
logical one.
LOW V WRITE INHIBIT
CC
When VCC is less than VLKO, the device does not accept
any write cycles. This protects data during VCC power-up
and power-down. The command register and all internal
POWER-UP WRITE INHIBIT
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge of
program/erase circuits are disabled, and the device resets. WE#. The internal state machine is automatically reset
Subsequent writes are ignored until VCC is greater than
VLKO. The system must provide the proper signals to the
control pins to prevent unintentional writes when VCC is
greater than V .
LKO
to reading array data on power-up.
AS29LV016J
Rev. 0.0 02/09
16
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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