APW7060 View Datasheet(PDF) - Anpec Electronics
Part Name
Description
Manufacturer
APW7060 Datasheet PDF : 16 Pages
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APW7060
Application Information
where Iout is the maximum load current
Vout2 is the nominal output voltage
In some applications, heatsink maybe required to help
maintain the junction temperature of the MOSFET be-
low its maximum rating.
V DS
•
The
ground
return
of
C
IN
must
return
to
the
combine
C (-) terminal.
OUT
•
Capacitor
C is
HF
to
improve
noise
performance
and
a small 1uF ceramic capacitor will be sufficient. Place
this capacitor close of the drain of Q1.
• Inductor L1 should be connected closely to the
PHASE node.
• Bypass capacitors, CBP, should be placed as close
to the 5VCC and 12VCC pins.
t sw
Time
Figure 4. Switching waveform across MOSFET
Layout Considerations
In high power switching regulator, a correct layout is
important to ensure proper operation of the regulator.
In general, interconnecting impedances should be mini-
mized by using short, wide printed circuit traces. Sig-
nal and power grounds are to be kept separate and
finally combined using ground plane construction or
single point grounding. Figure 5 illustrates the layout,
with bold lines indicating high current paths. Compo-
nents along the bold lines should be placed close
together. Below is a checklist for your layout:
• Keep the switching nodes (UGATE, LGATE and
the PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals. There
fore keep traces to these nodes as short as
possible.
•
Decoupling
capacitor
C
IN
provides
the
bulk
capaci
tance and needs to be placed close to the drain of
Q1.
Copyright ANPEC Electronics Corp.
12
Rev. A.3 - Oct., 2003
VIN
5VCC
GND
GND
CHF
5VCC
CBP
+
CBP
CIN
12VCC
12VCC
UGATE
LGATE
Q1
Q2
APW7060
PHASE
L1
+ COUT
VOUT
Figure 5. Recommended Layout Diagram
www.anpec.com.tw
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