APA1000-CG256PP View Datasheet(PDF) - Actel Corporation

Part Name

Description

Manufacturer

APA1000-CG256PP

ProASICPLUS® Flash Family FPGAs

Actel Corporation 

ProASICPLUS Flash Family FPGAs

In 1

In 2 (CLK)

Local Routing

Efficient Long-Line Routing

In 3 (Reset)

Figure 1-3 • Core Logic Tile

Live at Power-Up

The Actel flash-based ProASICPLUS devices support

Level 0 of the live at power-up (LAPU) classification

standard. This feature helps in system component

initialization, executing critical tasks before the

processor wakes up, setting up and configuring memory

blocks, clock generation, and bus activity management.

The LAPU feature of flash-based ProASICPLUS devices

greatly simplifies total system design and reduces total

system cost, often eliminating the need for complex

programmable logic device (CPLD) and clock generation

PLLs that are used for this purpose in a system. In

addition, glitches and brownouts in system power will

not corrupt the ProASICPLUS device's flash configuration,

and unlike SRAM-based FPGAs, the device will not have

to be reloaded when system power is restored. This

enables the reduction or complete removal of the

configuration PROM, expensive voltage monitor,

brownout detection, and clock generator devices from

the PCB design. Flash-based ProASICPLUS devices simplify

total system design, and reduce cost and design risk,

while increasing system reliability and improving system

initialization time.

Flash Switch

Unlike SRAM FPGAs, ProASICPLUS uses a live-at-power-up

ISP flash switch as its programming element.

In the ProASICPLUS flash switch, two transistors share the

floating gate, which stores the programming

information. One is the sensing transistor, which is only

used for writing and verification of the floating gate

voltage. The other is the switching transistor. It can be

used in the architecture to connect/separate routing nets

or to configure logic. It is also used to erase the floating

gate (Figure 1-2 on page 1-2).

Logic Tile

The logic tile cell (Figure 1-3) has three inputs (any or all

of which can be inverted) and one output (which can

connect to both ultra-fast local and efficient long-line

routing resources). Any three-input, one-output logic

function (except a three-input XOR) can be configured as

one tile. The tile can be configured as a latch with clear

or set or as a flip-flop with clear or set. Thus, the tiles can

flexibly map logic and sequential gates of a design.

v5.9

1-3

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