APA1000 View Datasheet(PDF) - Actel Corporation

Part Name

Description

Manufacturer

APA1000

ProASICPLUS® Flash Family FPGAs

Actel Corporation 

ProASICPLUS Flash Family FPGAs

The following is an APA750 example using a shift register design with 13,440 storage tiles (Register) and 0 logic tiles.

This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz. We then calculate the various components as

follows:

Pclock

Fs = 10 MHz

R = 13,440

=> Pclock = (P1 + (P2*R) - (P7*R2)) * Fs = 121.5 mW

Pstorage

ms = 13,440 (in a shift register 100% of storage tiles are toggling at each clock cycle and Fs = 10 MHz)

=> Pstorage = P5 * ms * Fs = 147.8 mW

Plogic

mc = 0 (no logic tiles in this shift register)

=> Plogic = 0 mW

Poutputs

Cload

VDDP

p

= 40 pF

= 3.3 V

= 24

Fp = 5 MHz

=> Poutputs = (P4 + (Cload * VDDP2)) * p * Fp = 91.4 mW

Pinputs

q

=1

Fq

= 10 MHz

=> Pinputs = P8 * q * Fq = 0.3 mW

Pmemory

Nmemory = 0 (no RAM/FIFO blocks in this shift register)

=> Pmemory = 0 mW

Pac

=> 361 mW

Ptotal

Pdc + Pac = 374 mW (typical)

2-30

v5.9

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