APA075-CQ144 View Datasheet(PDF) - Actel Corporation

Part Name

Description

Manufacturer

APA075-CQ144

ProASICPLUS® Flash Family FPGAs

Actel Corporation 

ProASICPLUS Flash Family FPGAs

PLL Electrical Specifications

Parameter

Frequency Ranges

Value TJ ≤ –40°C

Value TJ > –40°C

Notes

Reference Frequency fIN (min.)

2.0 MHz

1.5 MHz

Clock conditioning circuitry (min.) lowest input

frequency

Reference Frequency fIN (max.)

180 MHz

180 MHz

Clock conditioning circuitry (max.) highest input

frequency

OSC Frequency fVCO (min.)

60

24 MHz

Lowest output frequency voltage controlled

oscillator

OSC Frequency fVCO (max.)

180

180 MHz

Highest output frequency voltage controlled

oscillator

Clock Conditioning Circuitry fOUT (min.)

Clock Conditioning Circuitry fOUT (max.)

fIN ≤ 40 = 18 MHz

fIN > 40 = 16 MHz

180

6 MHz

180 MHz

Lowest output frequency clock conditioning

circuitry

Highest output frequency clock conditioning

circuitry

Acquisition Time from Cold Start

Acquisition Time (max.)

80 μs

Acquisition Time (max.)

80 μs

Long Term Jitter Peak-to-Peak Max.*

30 μs

80 μs

fVCO ≤ 40 MHz

fVCO > 40 MHz

Temperature

Frequency MHz

25°C (or higher)

fVCO< 10<fV fVCO

10 CO<60 >60

±1% ±2% ±1% Jitter(ps) = Jitter(%)*period

For example:

Jitter in picoseconds at 100 MHz

= 0.01 * (1/100E6) = 100 ps

0°C

±1.5% ±2.5% ±1%

–40°C

±2.5% ±3.5% ±1%

–55°C

±2.5% ±3.5% ±1%

Power Consumption

Analog Supply Power (max.*)

Digital Supply Current (max.)

6.9 mW per PLL

7 μW/MHz

Duty Cycle

50% ±0.5%

Input Jitter Tolerance

5% input period (max. Maximum jitter allowable on an input

5 ns)

clock to acquire and maintain lock.

Note: *High clock frequencies (>60 MHz) under typical setup conditions

2-18

v5.9

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