APA150-CQG1152 View Datasheet(PDF) - Actel Corporation

Part Name

Description

Manufacturer

APA150-CQG1152

ProASICPLUS® Flash Family FPGAs

Actel Corporation 

ProASICPLUS Flash Family FPGAs

Timing Control and

Characteristics

ProASICPLUS Clock Management System

ProASICPLUS devices provide designers with very flexible

clock conditioning capabilities. Each member of the

ProASICPLUS family contains two phase-locked loop (PLL)

blocks which perform the following functions:

• Clock Phase Adjustment via Programmable Delay

(250 ps steps from –7 ns to +8 ns)

• Clock Skew Minimization

• Clock Frequency Synthesis

Each PLL has the following key features:

• Input Frequency Range (fIN) = 1.5 to 180 MHz

• Feedback Frequency Range (fVCO) = 24 to 180 MHz

• Output Frequency Range (fOUT) = 8 to 180 MHz

• Output Phase Shift = 0 ° and 180 °

• Output Duty Cycle = 50%

• Low Output Jitter (maximum at 25°C)

– fVCO <10 MHz. Jitter ±1% or better

– 10 MHz < fVCO < 60 MHz. Jitter ±2% or better

– fVCO > 60 MHz. Jitter ±1% or better

Note: Jitter (ps) = Jitter (%) × period

For Example:

Jitter in picoseconds at 100 MHz = 0.01 × (1/100E6) = 100 ps

• Maximum Acquisition = 80 µs for fVCO > 40 MHz

Time

= 30 µs for fVCO < 40 MHz

• Low Power Consumption – 6.9 mW (max. – analog

supply) + 7.0 µW/MHz (max. – digital supply)

Physical Implementation

Each side of the chip contains a clock conditioning circuit

based on a 180 MHz PLL block (Figure 2-11 on page

2-11). Two global multiplexed lines extend along each

side of the chip to provide bidirectional access to the PLL

on that side (neither MUX can be connected to the

opposite side's PLL). Each global line has optional LVPECL

input pads (described below). The global lines may be

driven by either the LVPECL global input pad or the

outputs from the PLL block, or both. Each global line can

be driven by a different output from the PLL. Unused

global pins can be configured as regular I/Os or left

unconnected. They default to an input with pull-up. The

two signals available to drive the global networks are as

follows (Figure 2-12 on page 2-12, Table 2-7 on page 2-

12, and Table 2-8 on page 2-13):

Global A (secondary clock)

• Output from Global MUX A

• Conditioned version of PLL output (fOUT) – delayed

or advanced

• Divided version of either of the above

• Further delayed version of either of the above

(0.25 ns, 0.50 ns, or 4.00 ns delay)1

Global B

• Output from Global MUX B

• Delayed or advanced version of fOUT

• Divided version of either of the above

• Further delayed version of either of the above

(0.25 ns, 0.50 ns, or 4.00 ns delay)2

Functional Description

Each PLL block contains four programmable dividers as

shown in Figure 2-11 on page 2-11. These allow

frequency scaling of the input clock signal as follows:

• The n divider divides the input clock by integer

factors from 1 to 32.

• The m divider in the feedback path allows

multiplication of the input clock by integer factors

ranging from 1 to 64.

• The two dividers together can implement any

combination of multiplication and division

resulting in a clock frequency between 24 and 180

MHz exiting the PLL core. This clock has a fixed

50% duty cycle.

• The output frequency of the PLL core is given by

the formula in EQ 2-1 (fREF is the reference clock

frequency):

fOUT = fREF × m ÷ n

EQ 2-1

• The third and fourth dividers (u and v) permit the

signals applied to the global network to each be

further divided by integer factors ranging from 1

to 4.

The implementations shown in EQ 2-2 and EQ 2-3 enable

the user to define a wide range of frequency multiplier

and divisors.

fGLB = (---n----m-×----u----)-

fGLA

=

-------m---------

(n × v)

EQ 2-2

EQ 2-3

1. This mode is available through the delay feature of the global MUX driver.

2-10

v5.9

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